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| "3@3 +:77@ Cologne Chip 752B\X]X 8B3=!13B 8B3=73;2585>R^]ca^[[Ta fXcW BCX]cTaUPRT P]S X]cTVaPcTS585>b 0dVdbc! Copyright 1994-2001 Cologne Chip AG All Rights Reserved The information presented can not be considered as assured characteristics. Data can change without notice. Parts of the information presented may be protected by patent or other rights. Cologne Chip products are not designed, intended, or authorized for use in any application intended to support or sustain life, or for any other application in which the failure of the Cologne Chip product could create a situation where personal injury or death may occur. 863C ]Y^Y Cologne Chip Revision History Date Aug. 2001 Jul. 2001 Jan. 2001 Nov. 2000 Remarks Chapters added: Timing diagrams for Motorala mode (mode2), Sample circuitries. Information added to: Register description. Information added to: Microprocessor access, PCM/GCI/IOM2 timing. preliminary edition. Cologne Chip Cologne Chip AG Eintrachtstrasse 113 D-50668 Koln Germany Tel.: +49 (0) 221 / 91 24-0 Fax: +49 (0) 221 / 91 24-100 http://www.CologneChip.com http://www.CologneChip.de info@CologneChip.com " _V '( 1eWecd " ! 863C ]Y^Y Cologne Chip Contents Features........................................................................................................................................................ 6 1 General description............................................................................................................................ 6 1.1 Block diagram.................................................................................................................................. 7 1.2 Applications ..................................................................................................................................... 7 1.3 Processor interface modes ............................................................................................................... 8 2 Pin description.................................................................................................................................... 9 2.1 S/T interface transmit signals .......................................................................................................... 9 2.2 S/T interface receive signals............................................................................................................ 9 2.3 PCM bus interface signals ............................................................................................................. 10 2.4 Processor interface signals............................................................................................................. 10 2.5 Miscellaneous pins......................................................................................................................... 11 2.6 Oscillator........................................................................................................................................ 11 2.7 Power supply.................................................................................................................................. 11 3 Functional description ..................................................................................................................... 12 3.1 Microprocessor interface ............................................................................................................... 12 3.1.1 Register access ...................................................................................................................... 12 3.2 FIFOs ............................................................................................................................................. 13 3.2.1 FIFO channel operation......................................................................................................... 14 3.2.1.1 Send channels (B1, B2, D and PCM transmit) ................................................................. 15 3.2.1.2 Automatically D-channel frame repetition ....................................................................... 15 3.2.1.3 FIFO full condition in send channels................................................................................ 16 3.2.1.4 Receive Channels (B1, B2, D and PCM receive) ............................................................. 16 3.2.1.5 FIFO full condition in receive channels ........................................................................... 17 3.2.2 FIFO initialization................................................................................................................. 18 3.2.3 FIFO reset.............................................................................................................................. 18 3.3 Transparent mode of HFC-S mini.................................................................................................. 19 3.4 Correspondency between FIFOs, CHANNELs and SLOTs.......................................................... 20 3.5 Subchannel Processing .................................................................................................................. 25 3.6 PCM Interface Function................................................................................................................. 26 3.7 Configuring test loops.................................................................................................................... 28 4 Register description ......................................................................................................................... 29 4.1 Register reference list .................................................................................................................... 29 4.1.1 Registers by address.............................................................................................................. 29 4.1.2 Registers by name ................................................................................................................. 30 4.2 FIFO, interrupt, status and control registers .................................................................................. 31 4.3 PCM/GCI/IOM2 bus section registers........................................................................................... 39 4.4 S/T section registers....................................................................................................................... 43 5 Electrical characteristics ................................................................................................................. 47 6 Timing characteristics ..................................................................................................................... 50 6.1 Microprocessor access ................................................................................................................... 50 6.1.1 Register read access in de-multiplexed Motorola mode (mode 2)........................................ 50 6.1.2 Register write access in de-multiplexed Motorola mode (mode 2) ...................................... 51 6.1.3 Register read access in de-multiplexed Intel mode (mode 3) ............................................... 52 6.1.4 Register write access in de-multiplexed Intel mode (mode 3) .............................................. 53 1eWecd " ! # _V '( 863C ]Y^Y Cologne Chip 6.1.5 Register read access in multiplexed mode (mode 4)............................................................. 54 6.1.6 Register write access in multiplexed mode (mode 4) ........................................................... 55 6.2 PCM/GCI/IOM2 timing................................................................................................................. 56 6.2.1 Master mode.......................................................................................................................... 57 6.2.2 Slave mode ............................................................................................................................ 58 7 External circuitries........................................................................................................................... 59 7.1 S/T interface circuitry.................................................................................................................... 59 7.1.1 External receiver circuitry..................................................................................................... 59 7.1.2 External wake-up circuitry.................................................................................................... 60 7.1.3 External transmitter circuitry ................................................................................................ 61 7.2 Oscillator circuitry for S/T clock................................................................................................... 64 8 State matrices for NT and TE ......................................................................................................... 65 8.1 S/T interface activation/deactivation layer 1 for finite state matrix for NT .................................. 65 8.2 Activation/deactivation layer 1 for finite state matrix for TE ....................................................... 66 9 Binary organisation of the frames .................................................................................................. 67 9.1 S/T frame structure ........................................................................................................................ 67 9.2 GCI frame structure ....................................................................................................................... 68 10 Clock synchronisation...................................................................................................................... 69 10.1 Clock synchronisation in NT-mode........................................................................................... 69 10.2 Clock synchronisation in TE-mode ........................................................................................... 70 10.3 Multiple HFC-S mini SYNC scheme ........................................................................................ 71 11 HFC-S mini package dimensions.................................................................................................... 72 12 Sample circuitries............................................................................................................................. 73 12.1 HFC-S mini in mode 2 (Motorola bus) ..................................................................................... 73 12.2 HFC-S mini in mode 3 (Intel bus with separated address bus/data bus)................................... 75 12.3 HFC-S mini in mode 4 (Intel bus with multiplexed address bus/data bus)............................... 77 $ _V '( 1eWecd " ! 863C ]Y^Y Cologne Chip Figures Figure 1: HFC-S mini block diagram............................................................................................................ 7 Figure 2: Pin Connection .............................................................................................................................. 9 Figure 3: FIFO Organisation....................................................................................................................... 14 Figure 4: FIFO Data Organisation .............................................................................................................. 16 Figure 5: FIFOs, CHANNELs and SLOTs in Transmit Direction ............................................................. 22 Figure 6: FIFOs, CHANNELs and SLOTs in Receive Direction............................................................... 23 Figure 7: Example for Subchannel Processing ........................................................................................... 25 Figure 8: PCM Interface Function Block Diagram..................................................................................... 26 Figure 9: Function of CON_HDLC register bits 7..5 ................................................................................. 37 Figure 10: External receiver circuitry......................................................................................................... 59 Figure 11: External wake-up circuitry ........................................................................................................ 60 Figure 12: External transmitter circuitry .................................................................................................... 61 Figure 13: Oscillator circuitry for S/T clock .............................................................................................. 64 Figure 14: Frame structure at reference point S and T ............................................................................... 67 Figure 15: Single channel GCI format........................................................................................................ 68 Figure 16: Clock synchronisation in NT-mode .......................................................................................... 69 Figure 17: Clock synchronisation in TE-mode ........................................................................................... 70 Figure 18: Multiple HFC-S mini SYNC scheme ........................................................................................ 71 Figure 19: HFC-S mini package dimensions .............................................................................................. 72 Tables Table 1: Function of the microprocessor interface control signals ............................................................ 12 Table 2: Possible connections of FIFOs and CHANNELs in Simple Mode (SM)..................................... 20 Table 3: CHANNEL Numbers on the S/T Interface and PCM Interface ................................................... 21 Table 4: S/T module part numbers and manufacturers............................................................................... 63 Table 5: Activation/deactivation layer 1 for finite state matrix for NT ..................................................... 65 Table 6: Activation/deactivation layer 1 for finite state matrix for TE...................................................... 66 Timing diagrams Timing diagram 1: Register read access in de-multiplexed Motorola mode (mode 2) .............................. 50 Timing diagram 2: Register write access in de-multiplexed Motorola mode (mode 2) ............................. 51 Timing diagram 3: Register read access in de-multiplexed Intel mode (mode 3) ...................................... 52 Timing diagram 4: Register write access in de-multiplexed Intel mode (mode 3)..................................... 53 Timing diagram 5: Register read access in multiplexed mode (mode 4) ................................................... 54 Timing diagram 6: Register write access in multiplexed mode (mode 4) .................................................. 55 Timing diagram 7: PCM/GCI/IOM2 timing ............................................................................................... 56 1eWecd " ! % _V '( 863C ]Y^Y Cologne Chip Features single chip ISDN-S/T-controller with B- and D-channel HDLC support integrated S/T interface full I.430 ITU S/T ISDN support in TE and NT mode for 3.3V and 5V power supply independent read and write HDLC-channels for 2 ISDN B-channels, one ISDN D-channel and one PCM timeslot (or E-channel) B1- and B2-channel transparent mode independently selectable integrated FIFOs for B1, B2, D and PCM (or E) FIFO size: 128 bytes per channel and direction; up to 7 HDLC frames per FIFO 56 kbit/s restricted mode for U.S. ISDN lines selectable by software PCM128 / PCM64 / PCM30 interface configurable to interface MITEL STTM bus (MVIPTM), Siemens IOM2TM or GCITM for interface to U-chip or external CODECs H.100 data rate supported microprocessor interface compatible to Motorola bus and Intel bus Timer with interrupt capability CMOS technology, 3V - 5V PQFP 48 case 1 General description The HFC-S mini is a single-chip ISDN S/T HDLC basic rate controller for embedded applications. The S/T interface, HDLC-controllers, FIFOs and a microprocessor interface are integrated in the HFC-S mini. A PCM128 / PCM64 / PCM30 interface is also implemented which can be connected to many telecom serial busses. CODECs are usually connected to this interface. All ISDN channels (2B+1D) and the PCM interface are served fully duplex by the 8 integrated FIFOs. HDLC controllers are implemented in hardware so there is no need to implement HDLC on the host processor. & _V '( 1eWecd " ! 863C ]Y^Y Cologne Chip 1.1 Block diagram TM 2x HDLC D-channel D-transmit D-receive 4x HDLC B-channel B1-transmit FIFOs B1-receive B2-transmit B2-receive PCM128/ PCM64/ PCM30 interface S/Tcontroller HFC - S mini S/T CODEC select PCM128 PCM64 PCM30 MST IOM2 GCI U-chip 2x HDLC PCM-trans. PCM-rec. U microprocessor interface microprocessor Figure 1: HFC-S mini block diagram 1.2 Applications The HFC-S mini can be used for all kinds of ISDN equipment with ISDN basic rate S/T interface. ISDN terminal adapters (for Internet access) ISDN terminal adapters (with POTS interfaces) ISDN PABX ISDN SoHo PABX (switching done by HFC-S mini) ISDN telephones ISDN video conferencing equipment ISDN dialers / LCR (Least Cost Routers) ISDN LAN Routers ISDN protocol analyzers ISDN smart NTs ! ' _V '( 1eWecd " 863C ]Y^Y Cologne Chip 1.3 Processor interface modes The HFC-S mini has an integrated 8-bit microprocessor interface which can be configured into Motorola bus, de-multiplexed Intel bus and multiplexed Intel bus. The different interface modes are selected during power on by ALE. Mode 2: Mode 3: Motorola bus with control signals /CS, R/W, /DS is selected by setting ALE to VDD. Intel bus with seperated address bus (A0) and data bus (D[7:0]) and control signals /CS, /WR, /RD is selected by setting ALE to GND. Intel bus with multiplexed address bus and data bus with control signals /CS, /WR, /RD, ALE. ALE must be '0' during power on to select this mode. A0 must be '0'. ALE latches the address. The multiplexed address/data bus is D[7:0]. Mode 4: In mode 4 all internal registers can be directly accessed. In mode 2 and mode 3 first the address of the desired register must be written to the address with A0 = '1'. Afterwards data can be read/written from/to that register by reading/writing the address with A0 = '0'. In mode 4 A0 must be '0'. ( _V '( 1eWecd " ! 863C ]Y^Y Cologne Chip 2 Pin description Figure 2: Pin Connection 2.1 S/T interface transmit signals Pin Name TX2_HI /TX1_LO /TX_EN /TX2_LO TX1_HI Input Output O O O O O Function Transmit output 2 GND driver for transmitter 1 Transmit enable GND driver for transmitter 2 Transmit output 1 Pin No. 13 14 15 16 17 2.2 20 21 22 23 25 28 S/T interface receive signals R2 LEV_R2 LEV_R1 R1 ADJ_LEV AWAKE I I I I O I Receive data 2 Level detect for R2 Level detect for R1 Receive data 1 Level generator Awake input pin for external awake circuitry 1eWecd " ! ) _V '( 863C ]Y^Y Cologne Chip 2.3 30 PCM bus interface signals C4IO I/O u) I/O u) 4.096 MHz / 8.192 MHz / 16.384 MHz clock PCM/GCI/IOM2 bus clock master: output PCM/GCI/IOM2 bus clock slave: input (reset default) Frame synchronisation, 8kHz pulse for PCM/GCI/IOM2 bus frame synchronisation PCM/GCI/IOM2 bus master: output PCM/GCI/IOM2 bus slave: input (reset default) PCM/GCI/IOM2 bus data line I Slotwise programmable as input or output PCM/GCI/IOM2 bus data line II Slotwise programmable as input or output enable signal for external CODEC A or C2IO clock (bit clock) Programmable as positive (reset default) or negative pulse. enable signal for external CODEC B Programmable as positive (reset default) or negative pulse. 31 F0IO 32 33 34 35 STIO1 STIO2 F1_A F1_B I/O u) I/O u) O O u) internal pull up 2.4 Processor interface signals Pin Name D0 D1 D2 D3 D4 D5 D6 D7 A0 /WR R/W /RD /DS /CS ALE Input Output I/O I/O I/O I/O I/O I/O I/O I/O I I I I I I u) I u) O e) Mode Function all all all all all all all all 2, 3 3, 4 2 3, 4 2 all Data bus (bit 0) Data bus (bit 1) Data bus (bit 2) Data bus (bit 3) Data bus (bit 4) Data bus (bit 5) Data bus (bit 6) Data bus (bit 7) Address bit 0 from external processor Write signal from external processor (low active) Read/Write select (WR='0') Read signal from external processor (low active) I/O data strobe Chip select (low active) Address latch enable ALE is also used for mode selection during power on (see also 1.3 Processor interface mode on page 8). Wait signal for external processor (low active) Pin No. 4 5 6 7 8 9 10 11 47 2 1 46 45 36 u) e) /WAIT all internal pull up external pull up required 1eWecd " ! ! _V '( 863C ]Y^Y Cologne Chip 2.5 Miscellaneous pins Pin Name SYNC_I SYNC_O NC /INT /RES Input Output I O O I u) Function 8 kHz sync input 8 kHz sync output Not connected (pin must be left open) Interrupt request for external processor (low active) Reset (low active) Pin No. 38 43 42 44 48 u) internal pull up 2.6 Oscillator Pin Name CLKI CLKO Input Output I O Function 24.576 MHz clock input or 24.576 MHz crystal 24.576 MHz clock output or 24.576 MHz crystal Pin No. 26 27 2.7 Power supply Pin No. Pin Name VDD GND Function VDD (3.3V or 5V) GND 3, 19, 40 12, 18, 24, 29, 37, 39, 41 1eWecd " ! !! _V '( 863C ]Y^Y Cologne Chip 3 3.1 Functional description Microprocessor interface The HFC-S mini has an integrated 8 bit microprocessor interface. It is compatibel with Motorola bus and Intel bus. The different microprocessor interface modes are selected during power on by ALE (see also 1.3 Processor interface modes on page 8). In mode 2 (Motorola bus mode) and mode 3 (de-multiplexed Intel bus mode) pin A0 is the address input. The data bus is D[7:0]. In mode 4 (multiplexed Intel bus mode) D[7:0] is the multiplexed address/data bus. A0 must be '0' in this mode. 3.1.1 Register access In mode 2 and mode 3 the HFC-S mini has 2 addresses. The lower address (A0 = '0') is used for data read/write. The higher address (A0 = '1') is write only and is used for register selection. Registers are selected by first setting A0 to '1' and then writing the address of the desired register to the data bus D[7:0]. All following accesses to the HFC-S mini with A0 = '0' are read/write operations to this register. In mode 4 all registers can be directly accessed by their address. The function of the control signals is shown in the table below. /RD /DS X 1 0 0 0 1 0 1 /WR R/W X 1 1 0 1 0 1 0 /CS 1 X 0 0 0 0 0 0 ALE X X 1 1 0 0 0*) 0*) Operation no access no access read data write data read data write data read data write data Mode all all 2 2 3 3 4 4 Table 1: Function of the microprocessor interface control signals X = don't care *) 1-pulse latches register address. Except in mode 4 ALE is assumed to be stable after RESET. !" _V '( 1eWecd " ! 863C ]Y^Y Cologne Chip 3.2 FIFOs There is a transmit and a receive FIFO with HDLC-controller for each of the two B-channels, for the Dchannel and for the PCM interface in the HFC-S mini. Each FIFO has 128 bytes length in each direction. Up to 7 frames can be stored in each FIFO. The HDLC circuits are located on the S/T device side of the HFC-S mini. So always plain data is stored in the FIFOs. Zero insertion and CRC checksum processing for receive and transmit data is done by the HFC-S mini automatically. A FIFO can be selected for access by writing its number in the FIFO select register (FIFO#). The FIFOs are ring buffers. To control them there are some counters. Z1 is the FIFO input counter and Z2 is the FIFO output counter. Each counter points to a byte position in the SRAM. On a FIFO input operation Z1 is incremented. On an output operation Z2 is incremented. After every pulse on the F0IO signal two HDLC-bytes are written into the S/T interface (FIFOs with even numbers) and two HDLC-bytes are read from the S/T interface (FIFOs with odd numbers). D-channel data is handled in a similar way but only 2 bits are processed. * important! Instead of the S/T interface also PCM bus is selectable for each B-channel (see CON_HDLC register). If Z1 = Z2 the FIFO is empty. Additionally there are two counters F1 and F2 for every FIFO channel (3 bits for each channel). They count the HDLC-frames in the FIFOs and form a ring buffer as Z1 and Z2 do, too. F1 is incremented when a complete frame has been received and stored in the FIFO. F2 is incremented when a complete frame has been read from the FIFO. If F1 = F2 there is no complete frame in the FIFO. When the RESET line is active or software reset is active Z1, Z2, F1 and F2 are all initialized to all 1s (so Z-counters are initialized to 7Fh and F-counters are initialized to 07h). The access to a FIFO is selected by writing the FIFO number into the FIFO select register (FIFO#). 1eWecd " ! !# _V '( 863C ]Y^Y Cologne Chip * important! FIFO change, FIFO reset and F1/F2 incrementation Changing the FIFO, reseting the FIFO or incrementing the frame counters causes a short BUSY period of the HFC-S mini. This means an access to FIFO control registers is NOT allowed until BUSY status is reset (bit 0 of STATUS register). This has a maximum duration of 25 clock cycles (2s). Status, interrupt and control registers can be read and written at any time. * important! The counter state 00h of the Z-counters follows counter state 7Fh in the B-, D- and PCM FIFOs. The counter state 00h of the F-counters follows counter state 07h in the B-, D- and PCM FIFOs. 3.2.1 FIFO channel operation Figure 3: FIFO Organisation !$ _V '( 1eWecd " ! 863C ]Y^Y Cologne Chip 3.2.1.1 Send channels (B1, B2, D and PCM transmit) The send channels send data from the host bus interface to the FIFO and the HFC-S mini converts the data into HDLC code and tranfers it from the FIFO into the S/T or/and the PCM bus interface write registers. The HFC-S mini checks Z1 and Z2. If Z1=Z2 (FIFO empty) the HFC-S mini generates a HDLC-Flag (01111110) or idle pattern (1111 1111) and sends it to the S/T device. In this case Z2 is not incremented. If also F1=F2 only HDLC flags are sent to the S/T interface and all counters remain unchanged. If the frame counters are unequal F2 is incremented and the HFC-S mini tries to send the next frame to the output device. After the end of a frame (Z2 reaches Z1) it automatically generates the 16 bit CRC checksum and adds the ending flag. If there is another frame in the FIFO (F1F2) the F2 counter is incremented. With every byte being sent from the host bus side to the FIFO Z1 is incremented automatically. If a complete frame has been sent F1 must be incremented to send the next frame. If the frame counter F1 is incremented also the Z-counters may change because Z1 and Z2 are functions of F1 and F2. So there are Z1(F1), Z2(F1), Z1(F2) and Z2(F2) (see Figure 3). Z1(F1) is used for the frame which is just written from the microprocessor bus side. Z2(F2) is used for the frame which is just beeing transmitted to the S/T device side of the HFC-S mini. Z1(F2) is the end of frame pointer of the current output frame. In the send channels F1 is only changed from the microprocessor interface side if the software driver wants to say end of send frame". Then the current value of Z1 is stored, F1 is incremented and Z1 is used as start address of the next frame. Z1(F2) and Z2(F2) can not be accessed. * important! The HFC-S mini begins to transmit the bytes from a FIFO at the moment the FIFO is changed or the F1 counter is incremented. Also changing to the FIFO that is already selected starts the transmission. So by selecting the same FIFO again transmission can be started. This is required if a HDLC frame is longer than 128 bytes. 3.2.1.2 Automatically D-channel frame repetition The D-channel send FIFO has a special feature. If the S/T interface signals a D-channel contention before the CRC is sent the Z2 counter is set to the starting address of the current frame and the HFC-S mini tries to repeat the frame automatically. 1eWecd " ! !% _V '( 863C ]Y^Y Cologne Chip 3.2.1.3 FIFO full condition in send channels There are two different FIFO full conditions. The first one is met when the FIFO contents comes up to 7 frames. There is no possibility for the HFC-S mini to manage more frames even if the frames are very small. The driver software must check that there are never more than 7 HDLC frames in a FIFO. The second limitation is the size of the FIFO (128 bytes each). FIFO full condition can be checked by reading the F_USAGE register. It shows the actually occupied FIFO space in bytes. Furthermore a threshold value can be set for all transmit and receive FIFOs in the F_THRES register. Then the F_FILL register shows an indication for the filling level for each FIFO. 3.2.1.4 Receive Channels (B1, B2, D and PCM receive) The receive channels receive data from the S/T or PCM bus interface read registers. The data is converted from HDLC into plain data and sent to the FIFO. The data can then be read via the microprocessor bus interface. The HFC-S mini checks the HDLC data coming in. If it finds a flag or more than 5 consecutive 1s it does not generate any output data. In this case Z1 is not incremented. Proper HDLC data being received is converted by the HFC-S mini into plain data. After the ending flag of a frame the HFC-S mini checks the HDLC CRC checksum. If it is correct one byte with all 0s is inserted behind the CRC data in the FIFO named STAT. This last byte of a frame in the FIFO is different from all 0s if there is no correct CRC field at the end of the frame. Figure 4: FIFO Data Organisation !& _V '( 1eWecd " ! 863C ]Y^Y Cologne Chip The ending flag of a HDLC-frame can also be the starting flag of the next frame. After a frame is received completely F1 is incremented by the HFC-S mini automatically and the next frame can be received. After reading a frame via the microprocessor bus interface F2 must be incremented. If the frame counter F2 is incremented also the Z-counters may change because Z1 and Z2 are functions of F1 and F2. So there are Z1(F1), Z2(F1), Z1(F2) and Z2(F2) (see Figure 3). Z1(F1) is used for the frame which is just received from the S/T device side of the HFC-S mini. Z2(F2) is used for the frame which is just beeing transmitted to the microprocessor bus interface. Z1(F2) is the end of frame pointer of the current output frame. To calculate the length of the current receive frame the software has to evaluate Z1-Z2+1. When Z2 reaches Z1 the complete frame has been read. In the receive channels F2 must be incremented from the microprocessor bus interface side after the software detects an end of receive frame (Z1=Z2) and F1F2. Then the current value of Z2 is stored, F2 is incremented and Z2 is copied as start address of the next frame. If Z1 = Z2 and F1 = F2 the FIFO is totally empty. Z1(F1) can not be accessed. * important! Before reading a FIFO a change FIFO operation (see also: FIFO# register) must be done even if the desired FIFO is already selected. The change FIFO operation is required to update the internal buffer of the HFC-S mini. Otherwise the first byte of the FIFO will be taken from the internal buffer and may be invalid. 3.2.1.5 FIFO full condition in receive channels Because the ISDN-B-channels and the ISDN-D-channels have no hardware based flow control there is no possibility to stop input data if a receive FIFO is full. So there is no FIFO full condition implemented in the HFC-S mini. The HFC-S mini assumes that the FIFOs are so deep that the host processors hard- and software is able to avoid any overflow of the receive FIFOs. Overflow conditions are again more than 7 input frames or a real overflow of the FIFO because of excessive data (more than 128 bytes). Because HDLC procedures only know a window size of 7 frames no more than 7 frames are sent without software intervention. The register F_FILL indicates if the fill level of some FIFOs exceeds the number of bytes defined in the F_THRES register. A byte overflow can be avoided by polling this register. However to avoid any undetected FIFO overflows the software driver should check the number of frames in the FIFO which is F1-F2. An overflow exists if the number (F1-F2) is less than the number in the last reading even if there was no reading of a frame in between. After a detected FIFO overflow condition this FIFO must be reset by setting the FIFO reset bit in the INC_RES_F register. 1eWecd " ! !' _V '( 863C ]Y^Y Cologne Chip 3.2.2 FIFO initialization After reset all FIFOs are disabled. To enable a FIFO at least one of bits[4:1] of the CON_HDLC register for the corresponding FIFO must be set to '1'. For D-channel FIFOs the inter frame fill bit (bit 0 of CON_HDLC register) must be set to '1'. The HDLC_PAR register must be set to 02h ('0000 0010'). 3.2.3 FIFO reset All counters Z1, Z2, F1 and F2 of all FIFOs are initialized to all 1s after a RESET. Then the result is Z1 = Z2 = 7Fh and F1 = F2 = 07h. The same initialisation is done if the bit 3 in the CIRM register is set (soft reset). Single FIFOs can be reset by setting bit 1 of INC_RES_F register. !( _V '( 1eWecd " ! 863C ]Y^Y Cologne Chip 3.3 Transparent mode of HFC-S mini You can switch off HDLC operation for each B-channel independently. There is one bit for each Bchannel in the CON_HDLC control register. If this bit is set data in the FIFO is sent directly to the S/T or PCM bus interface and data from the S/T or PCM bus interface is sent directly to the FIFO. The FIFOs should be empty when switching into transparent mode. If a send FIFO channel changes to FIFO empty condition no CRC is generated and the last data byte in the FIFO memory is repeated until there is new data. If the last data byte which was written to the selected FIFO should be repeated the last byte must be written without increment of Z-counter (FIF_DATA register, address 84h). In receive channels there is no check on flags or correct CRCs and no status byte is added. The byte bounderies are not arbitrary like in HDLC mode where byte synchronisation is achieved with HDLC-flags. The data is just the same as it comes from the S/T or PCM bus interface or is sent to this. Send and receive transparent data can be handled in two ways. The usual way is transporting B-channel data with the LSB first as it is usual in HDLC mode. The second way is sending the bytes in reverse bit order as it is usual for PWM data. So the first bit is the MSB. The bit order can be reversed by setting the corresponding bit in the F_CROSS register. 1eWecd " ! !) _V '( 863C ]Y^Y Cologne Chip 3.4 Correspondency between FIFOs, CHANNELs and SLOTs For the data processing of the HFC-S mini you must distinguish between FIFOs, CHANNELs and SLOTs. The FIFOs are buffers between the microprocessor interface and the data interfaces PCM and/or S/T. The HDLC controllers are located on the non host bus side of the FIFOs. The CHANNELs are either mapped to the data channels on the S/T interface (then the CHANNEL selects the S/T channel as shown in Table 3) or they can be connected to arbitrary timeslots on the PCM interface. SLOTs are 8 bit timeslots on the PCM interface. The following values (registers) characterise FIFOs, CHANNELs and SLOTs: FIFO: FIFO# CHANNEL: CHANNEL# SLOT: B1_RSL, B1_SSL, B2_RSL, B2_SSL, AUX1_RSL, AUX1_SSL, AUX2_RSL and AUX2_SSL Even numbers (LSB = '0') always belong to a transmit FIFO, transmit CHANNEL (see also: Table 3). Odd numbers (LSB = '1') always belong to a receive FIFO, receive CHANNEL (see also: Table 3). In Simple Mode (F_MODE register bit 7 = '0', SM) the CHANNEL number equals the FIFO number. But it is possible to connect each FIFO to a PCM timeslot instead of the S/T interface in this mode (see table below). FIFO-No. (FIFO#, bits 2..0) '000' '001' '010' '011' '100' '101' '110' '111' CHANNEL after RESET Possible Connections in Simple Mode (SM) (CON_HDLC, bits 7..5) B1-transmit channel (S/T) B1-transmit channel (S/T) PCM-transmit timeslot selected by B1_SSL B1-receive channel (S/T) B1-receive channel (S/T) PCM-receive timeslot selected by B1_RSL B2-transmit channel (S/T) B2-transmit channel (S/T) PCM-transmit timeslot selected by B2_SSL B2-receive channel (S/T) B1-receive channel (S/T) PCM-receive timeslot selected by B2_RSL D-transmit channel (S/T) D-transmit channel (S/T) PCM-transmit timeslot selected by AUX1_SSL D-receive channel (S/T) D-receive channel (S/T) PCM-receive timeslot selected by AUX1_RSL invalid (E is receive only) PCM-transmit timeslot selected by AUX2_SSL E-receive channel (S/T) E-receive channel (S/T) PCM-receive timeslot selected by AUX2_RSL Table 2: Possible connections of FIFOs and CHANNELs in Simple Mode (SM) " _V '( 1eWecd " ! 863C ]Y^Y Cologne Chip In Channel Select Mode (F_MODE register bit 7 = '1', CSM) FIFOs can be associated with arbitrary CHANNELs. FIFOs are selected by writing their number in the FIFO# register. All FIFOs are disabled after initialization (reset). By setting at least one of the CON_HDLC register bits 3..1 to '1' the selected FIFO is enabled. The connection between a FIFO and a CHANNEL can be established by the CHANNEL# register for each FIFO if Channel Select Mode is enabled (F_MODE register bit 7 = '1', CSM). Otherwise the CHANNEL number equals the FIFO number. The channels on the S/T interface (B1, B2, D and E) and PCM interface (B1, B2, AUX1 and AUX2) are numbered as follows: CHANNEL Number (CHANNEL#, bits 2..0) '000' '001' '010' '011' '100' '101' '110' '111' ISDN Channel on the S/T Interface B1-transmit B1-receive B2-transmit B2-receive D-transmit D-receive invalid (E is receive only) E-receive ISDN Channel on the PCM Interface B1-transmit B1-receive B2-transmit B2-receive AUX1-transmit AUX1-receive AUX2-transmit AUX2-receive Table 3: CHANNEL Numbers on the S/T Interface and PCM Interface The data flow between the HFC part (FIFOs), S/T interface and PCM interface can be selected by the CON_HDLC register (bits 7..5) for each FIFO. The PCM timeslot for B1, B2, AUX1 and AUX2 can be specified by the timeslot assigner (registers B1_RSL, B1_SSL, B2_RSL, B2_SSL, AUX1_RSL, AUX1_SSL, AUX2_RSL and AUX2_SSL). Data of a CHANNEL can furthermore be looped over the PCM interface (and the timeslot assigner). 1eWecd " ! "! _V '( 863C ]Y^Y Cologne Chip [T4] Select PCM Slot No. for Transmit Channel [T1] Transmit Channel for FIFO [T3] [T2] Select Data Bit Count / Start Bit / Flow for Mask Bits for Transmit Channel Transmit Channel CHANNEL PCM SLOT HDLC Data FIFOs Transparent Data CHANNEL Number FIFO Number SubChannel Processing CONNECT MEMORY see also: PCM Interface Function S/T Figure 5: FIFOs, CHANNELs and SLOTs in Transmit Direction [T1] In Simple Mode (SM) the CHANNEL number is the same as the FIFO number. If Channel Select Mode (CSM) is enabled the transmit CHANNEL for a FIFO can be selected by 1) writing the FIFO number (0..7) in the FIFO# register 2) writing the desired CHANNEL number (0..7) to the CHANNEL# register (bits 2..0) Please note that transmit CHANNELs are even numbered (bit 0 of CHANNEL# register = '0'). The bit values for the not processed bits of the transmit CHANNEL are read from the CH_MASK register. The processed bits are taken from the FIFO (see also: Subchannel Processing). Please note that more than one FIFO can transmit data to the same CHANNEL. This is useful to combine subchannels and transmit them in one ISDN channel. Data can either be transmitted to the S/T interface or the PCM interface. 1) write the FIFO number (0..7) in the FIFO# register 2) write the desired connection to the CON_HDLC register bits 7..5 The CON_HDLC register bits 7..5 settings must be the same for corresponding receive and transmit FIFOs. [T2] [T3] "" _V '( 1eWecd " ! 863C ]Y^Y Cologne Chip [T4] A PCM SLOT can be connected to a CHANNEL. FIFO-No. (FIFO#, bits 2..0) '000' '001' '010' '011' '100' '101' '110' '111' Register for Timeslot Selection B1_SSL B1_RSL B2_SSL B2_RSL AUX1_SSL AUX1_RSL AUX2_SSL AUX2_RSL The PCM SLOT number for a FIFO can be selected by writing the desired SLOT number to its timeslot selection register shown in the table above. Please note that only the *_SSL registers are for transmit slots. [R4] Select PCM Slot No. for Receive Channel [R1] Receive Channel for FIFO [R2] Bit Count / Start Bit / Mask Bits for Receive Channel [R3] Select Data Flow for Receive Channel CHANNEL PCM SLOT HDLC Data FIFOs Transparent Data CHANNEL Number FIFO Number SubChannel Processing CONNECT MEMORY see also: PCM Interface Function S/T Figure 6: FIFOs, CHANNELs and SLOTs in Receive Direction 1eWecd " ! "# _V '( 863C ]Y^Y Cologne Chip [R1] In Simple Mode (SM) the CHANNEL number is the same as the FIFO number. If Channel Select Mode (CSM) is enabled the transmit CHANNEL for a FIFO can be selected by 1) writing the FIFO number (0..7) in the FIFO# register 2) writing the desired CHANNEL number (0..7) to the CHANNEL# register (bits 2..0) Please note that receive CHANNELs are odd numbered (bit 0 of CHANNEL# register = '1'). The bit values of the not processed bits of the receive CHANNEL are ignored. The processed bits are taken from the CHANNEL (see also: Subchannel Processing). Please note that more than one FIFO can receive data from the same CHANNEL (e.g. bits 1..0 are processed by FIFO 1 and bits 3..2 by FIFO 3). This is useful to split subchannels that have been combined to be transmitted in one ISDN channel. [R2] [R3] Data can either be received from the S/T interface or the PCM interface. 1) write the FIFO number (0..7) in the FIFO# register 2) write the desired connection to the CON_HDLC register bits 7..5 The CON_HDLC register bits 7..5 settings must be the same for corresponding receive and transmit FIFOs. [R4] A PCM SLOT can be connected to a CHANNEL. FIFO-No. (FIFO#, bits 2..0) '000' '001' '010' '011' '100' '101' '110' '111' Register for Timeslot Selection B1_SSL B1_RSL B2_SSL B2_RSL AUX1_SSL AUX1_RSL AUX2_SSL AUX2_RSL The PCM SLOT number for a FIFO can be selected by writing the desired SLOT number to its timeslot selection register shown in the table above. Please note that only the *_RSL registers are for receive slots. "$ _V '( 1eWecd " ! 863C ]Y^Y Cologne Chip 3.5 Subchannel Processing The following example shows how subchannel processing can be configured by the HDLC_PAR register. Example: CHANNEL 0 CHANNEL 1 7 6 CHANNEL 2 CHANNEL 3 5 4 3 2 1 0 CHANNEL 4 CHANNEL 5 (Transmit Channels) (Receive Channels) Start Bit = 2 Bit Count = 3 Processed Bits Not Processed Bits (For transmit CHANNELs these bits are taken from the CH_MASK register.) Figure 7: Example for Subchannel Processing The start bit can be selected by bits 5..3 of the HDLC_PAR register. The number of bits to process can be selected by bits 2..0 of the HDLC_PAR register. By default (HDLC_PAR = 00h) all 8 bits are processed. In the given example the start bit is bit 2 and the number of bits to process is 3. The not processed bits are set to the value given in the CH_MASK register. Please note that the HDLC_PAR register settings can be different for each channel. 1eWecd " ! "% _V '( 863C ]Y^Y Cologne Chip 3.6 PCM Interface Function [1] Data Channel Select for Transmit Slot [2] STIO1 Output Buffer Enable for Transmit Slot CHANNEL CHANNEL DATA STIO1 SLOT CONNECT MEMORY [3] STIO2 Output Buffer Enable for Transmit Slot CHANNEL CHANNEL DATA A B A B STIO2 SLOT [6] Data Channel Select for Receive Slot [5] Loop MST Internally [4] Input Buffer Select for Receive Slot Figure 8: PCM Interface Function Block Diagram For Transmit Slots (B1_SSL, B2_SSL, AUX1_SSL and AUX2_SSL Register) Number Function B1_SSL, B2_SSL, AUX1_SSL and AUX2_SSL Register Bits [1] Data Channel Select for Bits[4:0] are for timeslot selection. Transmit Slot [2] STIO1 Output Buffer Enable Bits[7:6] = '10' (STIO1 Output Buffer Enable) for Transmit Slot [3] STIO2 Output Buffer Enable Bits[7:6] = '11' (STIO2 Output Buffer Enable) for Transmit Slot "& _V '( 1eWecd " ! 863C ]Y^Y Cologne Chip For Receive Slots (B1_RSL, B2_RSL, AUX1_RSL and AUX2_RSL Register) Number Function B1_RSL, B2_RSL, AUX1_RSL and AUX2_RSL Register Bits [4] Input Buffer Select for Receive Bit 6 = '0' (Data In From STIO2 [MUX Input B]) Slot Bit 6 = '1' (Data In From STIO1 [MUX Input A]) [5] Loop MST Internally Bit 6 of MST_MODE1 Register '0' MUX Input B (Normal Operation) '1' MUX Input A (Internal Loop) [6] Data Channel Select for Bits[4:0] are for timeslot selection. Receive Slot 1eWecd " ! "' _V '( 863C ]Y^Y Cologne Chip 3.7 Configuring test loops For electrical tests of layer 1 it is useful to create a S/T test loop for the B1/B2 channel. The test loop described here transmits the data that has been received on the B1 or B2 channel to the same channel on the S/T interface. To configure the test loop the following must be done: - write 0Fh to register CLKDEL (37h) // Adjust the phase offset between receive and // transmit direction (the value depends on the external // circuitry). // 03h is to enable B1, B2 at the S/T interface for // transmission // 40h is for TX_LO setup (capacitive line mode) // Release S/T state machine for activation over the // S/T interface by incoming INFO 2 or INFO 4. // Configure S/T B1 and B2 channel to normal // receive operation. // Select B1 transmit // Configure B1 transmit channel for test loop // Select B1 receive // Configure B1 receive channel for test loop // Select B2 transmit // Configure B2 transmit channel for test loop // Select B2 receive // Configure B2 receive channel for test loop // Enable transmit channel for PCM/GCI/IOM2 bus, pin // STIO1 is used as output, use time slot #0. // Enable receive channel for PCM/GCI/IOM2 bus, pin // STIO1 is used as input, use time slot #0. // Enable transmit channel for PCM/GCI/IOM2 bus, pin // STIO1 is used as output, use transmission slot #1. // Enable receive channel for PCM/GCI/IOM2 bus, pin // STIO1 is used as input, use time slot #1. // Configure HFC-S mini as PCM/GCI/IOM2 bus master. - write 43h to register SCTRL (31h) - write 00h to register STATES (30h) - write 03h to register SCTRL_R (33h) - write 00h to register FIFO# (0Fh) write C4h to register CON_HDLC (FAh) write 01h to register FIFO# (0Fh) write C4h to register CON_HDLC (FAh) write 02h to register FIFO# (0Fh) write C4h to register CON_HDLC (FAh) write 03h to register FIFO# (0Fh) write C4h to register CON_HDLC (FAh) - write 80h to register B1_SSL (20h) - write C0h to register B1_RSL (24h) - write 81h to register B2_SSL (21h) - write C1h to register B2_RSL (25h) - write 01h to register MST_MODE0 (14h) "( _V '( 1eWecd " ! 863C ]Y^Y Cologne Chip 4 4.1 Register description Register reference list 4.1.1 Registers by address Registers by Address Name Address CIRM 00h FIF_Z1 [] 04h FIF_Z2 [] 06h RAM_ADR_L 08h RAM_ADR_H 09h RAM_DATA 0Ah F_CROSS 0Bh F_THRES 0Ch FIF_F1 [] 0Ch F_MODE 0Dh FIF_F2 [] 0Dh INC_RES_F [] 0Eh FIFO# 0Fh INT_S1 10h INT_S2 11h MST_MODE0 14h MST_MODE1 15h CHIP_ID 16h MST_MODE2 16h F0_CNT_L 18h F0_CNT_H 19h F_USAGE [] 1Ah INT_M1 1Ah F_FILL 1Bh INT_M2 1Bh STATUS 1Ch TIME_SEL 1Ch B1_SSL 20h B2_SSL 21h AUX1_SSL 22h AUX2_SSL 23h B1_RSL 24h B2_RSL 25h AUX1_RSL 26h Page 31 32 32 31 31 31 31 32 32 31 32 31 32 33 34 40 41 38 42 42 42 32 35 33 35 38 38 39 39 39 39 39 39 39 Registers by Address Name Address AUX2_RSL 27h C/I 28h TRxR 29h MON1_D 2Ah MON2_D 2Bh B1_D 2Ch B2_D 2Dh AUX1_D 2Eh AUX2_D 2Fh STATES 30h SCTRL 31h SCTRL_E 32h SCTRL_R 33h SQ_REC 34h SQ_SEND 34h CLKDEL 37h B1_REC 3Ch B1_SEND 3Ch B2_REC 3Dh B2_SEND 3Dh D_REC 3Eh D_SEND 3Eh E_REC 3Fh FIF_DATA [] 80h FIF_DATA [] 84h CH_MASK [] F4h CON_HDLC [] FAh HDLC_PAR [] FBh CHANNEL# [] FCh Page 39 42 42 42 42 39 39 39 39 43 44 44 45 45 45 45 46 46 46 46 46 46 46 32 32 37 36 35 37 1eWecd " ! ") _V '( 863C ]Y^Y Cologne Chip 4.1.2 Registers by name Registers by Name Name Address AUX1_D 2Eh AUX1_RSL 26h AUX1_SSL 22h AUX2_D 2Fh AUX2_RSL 27h AUX2_SSL 23h B1_D 2Ch B1_REC 3Ch B1_RSL 24h B1_SEND 3Ch B1_SSL 20h B2_D 2Dh B2_REC 3Dh B2_RSL 25h B2_SEND 3Dh B2_SSL 21h C/I 28h CH_MASK [] F4h CHANNEL# [] FCh CHIP_ID 16h CIRM 00h CLKDEL 37h CON_HDLC [] FAh D_REC 3Eh D_SEND 3Eh E_REC 3Fh F_CROSS 0Bh F_FILL 1Bh F_MODE 0Dh F_THRES 0Ch F_USAGE [] 1Ah F0_CNT_H 19h F0_CNT_L 18h Page 39 39 39 39 39 39 39 46 39 46 39 39 46 39 46 39 42 37 37 38 31 45 36 46 46 46 31 33 31 32 32 42 42 Registers by Name Name Address FIF_DATA [] 80h FIF_DATA [] 84h FIF_F1 [] 0Ch FIF_F2 [] 0Dh FIF_Z1 [] 04h FIF_Z2 [] 06h FIFO# 0Fh HDLC_PAR [] FBh INC_RES_F [] 0Eh INT_M1 1Ah INT_M2 1Bh INT_S1 10h INT_S2 11h MON1_D 2Ah MON2_D 2Bh MST_MODE0 14h MST_MODE1 15h MST_MODE2 16h RAM_ADR_H 09h RAM_ADR_L 08h RAM_DATA 0Ah SCTRL 31h SCTRL_E 32h SCTRL_R 33h SQ_REC 34h SQ_SEND 34h STATES 30h STATUS 1Ch TIME_SEL 1Ch TRxR 29h Page 32 32 32 32 32 32 32 35 31 35 35 33 34 42 42 40 41 42 31 31 31 44 44 45 45 45 43 38 38 42 # _V '( 1eWecd " ! 863C ]Y^Y Cologne Chip 4.2 Name CIRM FIFO, interrupt, status and control registers Addr. 00h r/w Function w unused, must be '0' w soft reset The reset is active until the bit is cleared. '0' deactivate reset (reset default) '1' activate reset 7..4 w unused, must be '0' 0Bh Select bit order for FIFO data '0' normal bit order (LSB first, reset default) '1' reverse bit order (MSB first) 0 w B1-transmit 1 w B1-receive 2 w B2-transmit 3 w B2- receive 4 w D-transmit 5 w D- receive 6 w PCM-transmit 7 w PCM-receive 0Dh 6..0 w must be '0' 7 w Channel Select Mode enable (CSM) 0Eh 0 w increment F-counter of selected FIFO ('1'=increment) 1 w reset selected FIFO ('1'=reset FIFO) 7..2 w unused, should be '0' 08h 7..0 w Address bits 7..0 for direct RAM access 09h 2..0 w Address bits 10..8 for direct RAM access 5..3 w must be '0' 6 w '1' reset address This bit is automatically cleared. 7 w '1' increment address after each read or write access to RAM_DATA 0Ah 7..0 r/w read/write RAM data FIFOs should be disabled before accessing the RAM directly. Bits 2..0 3 F_CROSS F_MODE INC_RES_F [FIFO#] RAM_ADR_L RAM_ADR_H RAM_DATA The registers RAM_ADR_H, RAM_ADR_L and RAM_DATA can be used for direct accesses to the internal FIFO-RAM. The FIFOs are located in the address range from 000h to 3FFh. Bits 2..0 of the address select the FIFO number, bits 10..4 are used to address the FIFO data. Before reading / writing data from / to a memory region all FIFOs using this region must be disabled. 1eWecd " ! #! _V '( 863C ]Y^Y Cologne Chip Name FIFO# Addr. 0Fh Bits 2..0 F_USAGE [FIFO#] FIF_DATA [FIFO#] 1Ah 80h 7..3 7..0 7..0 r/w Function w FIFO select '000' B1-transmit '001' B1-receive '010' B2-transmit '011' B2-receive '100' D-transmit '101' D-receive '110' PCM-transmit '111' PCM-receive w unused, should be '0' w fill level of FIFO in bytes r/w FIFO data register read/write data from/to the FIFO selected in the FIFO# register and increment Z-counter r/w FIFO data register (alternate) read/write data from/to the FIFO selected in the FIFO# register without incrementing Z-counter r FIFO input HDLC frame counter (F1) Up to 7 HDLC frames can be stored in each FIFO. r FIFO output HDLC frame counter (F2) Up to 7 HDLC frames can be stored in each FIFO. r FIFO input counter (Z1) Up to 128 bytes can be stored in one FIFO so the maximum value of the Z1 counter is 7Fh. r FIFO output counter (Z2) Up to 128 bytes can be stored in one FIFO so the maximum value of the Z2 counter is 7Fh. w transmit FIFO threshold for B1-transmit, B2-transmit, Dtransmit and PCM-transmit (see also F_FILL) '0000' 0 bytes '0001' 8 bytes (reset default) : : '1111' 120 bytes The corresponding bit(s) in the F_FILL register are set if the number of bytes in a transmit FIFO is greater or equal than this value. w receive FIFO threshold for B1-receive, B2-receive, D-receive and PCM-receive (see also F_FILL) '0000' 0 bytes '0001' 8 bytes (reset default) : : '1111' 120 bytes The corresponding bit(s) in the F_FILL register are set if the number of bytes in a receive FIFO is greater or equal than this value. 1eWecd " ! 84h 7..0 FIF_F1 [FIFO#] FIF_F2 [FIFO#] FIF_Z1 [FIFO#] FIF_Z2 [FIFO#] F_THRES 0Ch 0Dh 04h 7..0 7..0 7..0 06h 7..0 0Ch 3..0 7..4 #" _V '( 863C ]Y^Y Cologne Chip Name F_FILL INT_S1 Addr. Bits r/w Function 1Bh '0' Number of bytes in the following FIFOs is lower than the value defined in the F_THRES register. '1' Number of bytes in the following FIFOs is greater or equal than the value defined in the F_THRES register. 0 r B1-transmit 1 r B1-receive 2 r B2-transmit 3 r B2-receive 4 r D-transmit 5 r D-receive 6 r PCM-transmit 7 r PCM-receive 10h 0 r B1-channel interrupt status in transmit direction '1' a complete frame has been transmitted, the frame counter F2 has been incremented 1 r B1-channel interrupt status in receive direction '1' a complete frame has been transmitted, the frame counter F1 has been incremented 2 r B2-channel interrupt status in transmit direction '1' a complete frame has been transmitted, the frame counter F2 has been incremented 3 r B2-channel interrupt status in receive direction '1' a complete frame has been transmitted, the frame counter F1 has been incremented 4 r D-channel interrupt status in transmit direction '1' a complete frame was transmitted, the frame counter F2 was incremented 5 r D-channel interrupt status in receive direction '1' a complete frame was transmitted, the frame counter F1 was incremented 6 r PCM-channel interrupt status in transmit direction '1' a complete frame was transmitted, the frame counter F2 was incremented 7 r PCM-channel interrupt status in receive direction '1' a complete frame was transmitted, the frame counter F1 was incremented * note! The interrupts indicated in the INT_S1 register are frame interrupts which occur in HDLC mode. In transparent mode an interrupt can be generated on a regular basis. Interrupt frequency can be selected in the CON_HDLC register. 1eWecd " ! ## _V '( 863C ]Y^Y Cologne Chip Name INT_S2 Addr. 11h Bits 0 1 2 3 4 7..5 r/w Function r TE/NT state machine interrupt status '1' state of state machine changed r timer interrupt status '1' timer is elapsed r processing/non processing transition interrupt status '1' The HFC-S mini has changed from processing to non processing state. r GCI I-change interrupt '1' a different I-value on GCI was detected r receiver ready (RxR) of monitor channel '1' 2 monitor bytes have been received r unused, '0' * important! Reading the INT_S1 or INT_S2 register resets all active read interrupts in the INT_S1 or INT_S2 register respectively. New interrupts may occur during read. These interrupts are reported at the next read of INT_S1 or INT_S2. All interrupt bits are reported regardless of the mask registers settings (INT_M1 and INT_M2). The mask registers settings only influence the interrupt output condition. The interrupt output goes inactive during the read of INT_S1 or INT_S2. If interrupts occur during this read the interrupt line goes active immediately after the read is finished. So processors with level or transition triggered interrupt inputs can be connected. #$ _V '( 1eWecd " ! 863C ]Y^Y Cologne Chip Name INT_M1 Addr. 1Ah INT_M2 1Bh Bits 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 r/w w w w w w w w w w w w w w w w w Function interrupt mask for channel B1 in transmit direction interrupt mask for channel B1 in receive direction interrupt mask for channel B2 in transmit direction interrupt mask for channel B2 in receive direction interrupt mask for channel D in transmit direction interrupt mask for channel D in receive direction interrupt mask for channel PCM in transmit direction interrupt mask for channel PCM in receive direction interrupt mask for TE/NT state machine state change interrupt mask for timer interrupt mask for processing/non processing transition interrupt mask for GCI I-change interrupt mask for receiver ready (RxR) of monitor channel unused, must be '0' interrupt output is reversed enable interrupt output For mask bits a '1' enables and a '0' disables interrupt. RESET clears all bits to '0'. Name HDLC_PAR [FIFO#] Addr. FBh Bits 2..0 5..3 6 7 r/w Function w bit count for HDLC and transparent mode (number of bits to process) '000' process 8 bits (64kbit/s) (reset default) '001' process 1 bit : : '111' process 7 bits (56kbit/s) w start bit for HDLC and transparent mode '000' start processing with bit 0 (reset default) : : '111' start processing with bit 7 w FIFO loop '0' normal operation (reset default) '1' repeat current frame w invert data enable/disable '0' normal read/write data (reset default) '1' invert data * important! For B-channels the HDLC_PAR register must be set to 00h. To use 56kbit/s restricted mode the HDLC_PAR register must be set to 07h for B-channels. For D-channels the HDLC_PAR register must be set to 02h. 1eWecd " ! #% _V '( 863C ]Y^Y Cologne Chip Name CON_HDLC [FIFO#] Addr. FAh Bits 0 1 3..2 4 7..5 r/w Function w inter frame fill '0' write HDLC flags as inter frame fill (reset default) '1' write all '1's as inter frame fill (must be set for D-channel) w HDLC mode/transparent mode select '0' HDLC mode (reset default) '1' transparent mode select w transparent mode interrupt frequency if bits 3..1 are '0000' the FIFO is disabled select (reset default) '00' every 8 bytes '01' every 16 bytes '10' every 32 bytes '11' every 64 bytes w must be '0' w select data flow for selected FIFO destination source B1-channel (FIFO0 and 1, see FIFO#): bit 5: '0' FIFO1 B1-S/T '1' FIFO1 B1-PCM bit 6: '0' B1-S/T FIFO0 '1' B1-S/T B1-PCM bit 7: '0' B1-PCM FIFO0 '1' B1-PCM B1-S/T B2-channel (FIFO2 and 3, see FIFO#): bit 5: '0' FIFO3 B2-S/T '1' FIFO3 B2-PCM bit 6: '0' B2-S/T FIFO2 '1' B2-S/T B2-PCM bit 7: '0' B2-PCM FIFO2 '1' B2-PCM B2-S/T D-channel and PCM (FIFO4 and 5, see FIFO#): bit 5: '0' FIFO5 D-S/T '1' FIFO5 AUX1 bit 6: '0' D-S/T FIFO4 '1' D-S/T AUX1 bit 7: '0' AUX1 FIFO4 '1' AUX1 D-S/T E-channel and PCM (FIFO6 and 7, see FIFO#): bit 5: '0' FIFO7 E-S/T '1' FIFO7 AUX2 bit 6: '0' E-S/T FIFO6 '1' E-S/T AUX2 bit 7: '0' AUX2 FIFO6 '1' AUX2 E-S/T CON_HDLC register bits[7:5] must be the same for corresponding receive and transmit FIFOs. #& _V '( 1eWecd " ! 863C ]Y^Y Cologne Chip Figure 9: Function of CON_HDLC register bits 7..5 Name CH_MASK [FIFO#] CHANNEL# [FIFO#] Addr. F4h FCh Bits 7..0 2..0 7..3 r/w Function w Bit value for not processed bits of a channel. All not processed bits of a channel are set to the value defined in this register. w link selected FIFO to ISDN channel (only in Channel Select Mode (CSM), see F_MODE register) bit 2 bit 1 bit 0 link FIFO to S/T channel 0 0 0 B1-transmit 0 0 1 B1-receive 0 1 0 B2-transmit 0 1 1 B2-receive 1 0 0 D-transmit 1 0 1 D-receive 1 1 0 invalid (E is receive only) 1 1 1 E-receive w unused, must be '0' 1eWecd " ! #' _V '( 863C ]Y^Y Cologne Chip Name CHIP_ID Addr. 16h Bits 3..0 7..4 0 STATUS 1Ch 1 2 3 4 5 6 7 r/w Function r unused, '0' r Chip identification '0101' HFC-S mini r BUSY/NOBUSY status '1' the HFC-S mini is BUSY after initializing reset FIFO, increment F or change FIFO '0' the HFC-S mini is not busy, all accesses are allowed r processing/non processing status '1' the HFC-S mini is in processing phase (every 125s) '0' the HFC-S mini is not in processing phase r unused, '0' r AWAKE input signal r SYNC_I input signal r unused, '0' r an interrupt (with enabled mask bit) indicated in the INT_S2 register has occured r FRAME interrupt with enabled mask bit has occured (any data channel interrupt) All masked B-, D- and PCM-channel interrupts are "ored" (see register INT_S1) Reading the STATUS register clears no bit. Name TIME_SEL Addr. 1Ch Bits 3..0 7..4 r/w Function w select interrupt frequency of timer interrupt '0000' every 250s '0001' every 500s '0010' every 1ms '0011' every 2ms '0100' every 4ms '0101' every 8ms '0110' every 16ms '0111' every 32ms '1000' every 64ms '1001' every 128ms '1010' every 256ms '1011' every 512ms '1100' every 1024ms '1101' every 2048ms '1110' every 4096ms '1111' every 8192ms w unused, must be '0' #( _V '( 1eWecd " ! 863C ]Y^Y Cologne Chip 4.3 PCM/GCI/IOM2 bus section registers Timeslots for transmit direction Name B1_SSL B2_SSL AUX1_SSL AUX2_SSL Addr. 20h 21h 22h 23h Bits 4..0 5 6 r/w Function w select PCM/GCI/IOM2 bus transmission slot (0..31, 32..63, 64..95, 96..127, see MST_MODE2 register bits 5..4) w unused w select PCM/GCI/IOM2 bus data lines '0' STIO1 output '1' STIO2 output w transmit channel enable for PCM/GCI/IOM2 bus '0' disable (reset default) '1' enable 7 * important! Enabling more than one channel on the same slot causes undefined output data. Timeslots for receive direction Name B1_RSL B2_RSL AUX1_RSL AUX2_RSL Addr. 24h 25h 26h 27h Bits 4..0 5 6 r/w Function w select PCM/GCI/IOM2 bus receive slot (0..31, 32..63, 64..95, 96..127, see MST_MODE2 register bits 5..4) w unused w select PCM/GCI/IOM2 bus data lines '0' STIO2 is input '1' STIO1 is input w receive channel enable for PCM/GCI/IOM2 bus '0' disable (reset default) '1' enable 7 Data registers Name B1_D *) B2_D *) AUX1_D *) AUX2_D *) *) Addr. 2Ch 2Dh 2Eh 2Fh Bits 0..7 r/w Function r/w read/write data registers for selected timeslot data These registers are read/written automatically by the HDLC FIFO controller (HFC) or PCM controller and need not be accessed by the user. To read/write data the FIFO registers should be used. 1eWecd " ! #) _V '( 863C ]Y^Y Cologne Chip * note! Auxiliary channel handling To support an automatic codec to codec connection AUX1_D and AUX2_D can be set into mirror mode. In this case if the data registers AUX1_D and AUX2_D are not overwritten, the transmisson slots AUX1_SSL and AUX2_SSL mirror the data received in AUX1_RSL and AUX2_RSL slots. This is useful for an internal connection between two CODECs. This mirroring is enabled by setting bits 1..0 in MST_MODE1 register Configuration and status registers Name MST_MODE0 Addr. 14h Bits 0 r/w Function w PCM/GCI/IOM2 bus mode '0' slave (reset default) (C4IO and F0IO are inputs) '1' master (C4IO and F0IO are outputs) w polarity of C4- and C2O-clock '0' F0IO is sampled on negative clock transition '1' F0IO is sampled on positive clock transition w polarity of F0-signal '0' F0 positive pulse '1' F0 negative pulse w duration of F0-signal '0' F0 active for one C4-clock (244ns) (reset default) '1' F0 active for two C4-clocks (488ns) w time slot for codec-A signal F1_A '00' B1 receive slot '01' B2 receive slot '10' AUX1 receive slot '11' signal C2O pin F1_A (C2O is 1/2 C4O) time slot for codec-B signal F1_B '00' B1 receive slot '01' B2 receive slot '10' AUX1 receive slot '11' AUX2 receive slot 1 2 3 5..4 7..4 The pulse shape and polarity of the codec signals F1_A and F1_B is the same as the pulseshape of the F0IO signal. The polarity of C2O can be changed by bit 1. RESET sets register MST_MODE0, MST_MODE1 and MST_MODE2 to all '0's. * important! If no external clock source is connected to C4IO and F0IO bit 0 of MST_MODE0 must be set for normal operation. $ _V '( 1eWecd " ! 863C ]Y^Y Cologne Chip Name MST_MODE1 Addr. 15h Bits 0 1 3..2 5..4 6 7 r/w Function w enable/disable AUX1 channel mirroring '0' disable AUX1 channel data mirroring (reset default) '1' mirror AUX1 receive to AUX1 transmit w enable/disable AUX2 channel mirroring '0' disable AUX2 channel data mirroring (reset default) '1' mirror AUX2 receive to AUX2 transmit w DPLL adjust speed '00' C4IO clock is adjusted in the last time slot of MST frame 4 times by one half clock cycle '01' C4IO clock is adjusted in the last time slot of MST frame 3 times by one half clock cycle '10' C4IO clock is adjusted in the last time slot of MST frame twice by one half clock cycle '11' C4IO clock is adjusted in the last time slot of MST frame once by one half clock cycle w PCM data rate '00' 2MBit/s (PCM30) '01' 4MBit/s (PCM64) '10' 8MBit/s (PCM128) '11' unused w MST test loop When set MST output data is looped to the MST inputs. w enable PCM/GCI/IOM2 write slots '0' disable PCM/GCI/IOM2 write slots; slot #2 and slot #3 may be used for normal data '1' enables slot #2 and slot #3 as master, D- and C/I-channel 1eWecd " ! $! _V '( 863C ]Y^Y Cologne Chip Name MST_MODE2 Addr. 16h Bits 0 1 2 3 5..4 6 7 F0_CNT_L F0_CNT_H C/I 18h 19h 28h 7..0 7..0 3..0 7..4 0 1 5..2 6 7 7..0 7..0 TRxR 29h MON1_D MON2_D 2Ah 2Bh r/w Function w '1' generate frame signal for OKITM codecs on F1_A (see also PCM/GCI/IOM2 timing on page 56) w '1' generate frame signal for OKITM codecs on F1_B (see also PCM/GCI/IOM2 timing on page 56) w select PCM DPLL sync source '0' S/T receive frame (only in TE mode and state F7) '1' SYNC_I input 8 kHz w select SYNC_O output '0' S/T receive frame 8 kHz (only in TE mode and state F7) '1' SYNC_I is connected to SYNC_O w PCM/GCI/IOM2 slot select for higher data rates '00' slots 31..0 accessable '01' slots 63..32 accessable '10' slots 95..64 accessable '11' slots 127..96 accessable w This bit is only valid if bit 7 is set. '0' PCM frame time is reduced as selected by bits 3..2 of the MST_MODE1 register '1' PCM frame time is increased as selected by bits 3..2 of the MST_MODE1 register w '0' normal operation '1' enable PCM PLL adjust if no sync source is available r F0IO pulse count 16 bit 125s time counter (low byte) r F0IO pulse count 16 bit 125s time counter (high byte) r/w on read: indication on write: command unused r '1' Monitor receiver ready (2 monitor bytes have been received) r '1' Monitor transmitter ready Writing on MON2_D starts transmisssion and resets this bit. r reserved r STIO2 in r STIO1 in r/w first monitor byte r/w second monitor byte $" _V '( 1eWecd " ! 863C ]Y^Y Cologne Chip 4.4 S/T section registers Addr. 30h Bits 3..0 4 5 r/w r r r Function binary value of actual state (NT: Gx, TE: Fx) Frame-Sync ('1'=synchronized) '1' timer T2 expired (NT mode only, see also 8.1 S/T interface activation/deactivation layer 1 for finite state matrix for NT on page 65) '1' receiving INFO0 '1' in NT mode: transition from G2 to G3 is allowed. Set new state xxxx (bit 4 must also be set to load the state). '1' loads the prepared state (bit 3..0) and stops the state machine. This bit needs to be set for a minimum period of 5.21Ps and must be cleared by software. (reset default) '0' enables the state machine. After writing an invalid state the state machine goes to deactivated state (G1, F2) '00' no operation '01' no operation '10' start deactivation '11' start activation The bits are automatically cleared after activation/deactivation. '0' no operation '1' in NT mode: allows transition from G2 to G3. This bit is automatically cleared after the transition. Name STATES (read) STATES (write) 30h 6 7 3..0 4 r r w w 6..5 w 7 w * important! The S/T state machine is stuck to '0' after a reset. In this state the HFC-S mini sends no signal on the S/T-line and it is not possible to activate it by incoming INFOx. Writing a '0' to bit 4 of the STATES register restarts the state machine. NT mode: The NT state machine does not change automatically from G2 to G3 if the TE side sends INFO3 frames. This transition must be activated each time by bit 7 of the STATES register or by setting bit 0 of the SCTRL_E register. 1eWecd " ! $# _V '( 863C ]Y^Y Cologne Chip Name SCTRL Addr. 31h Bits 0 1 2 3 4 5 6 7 SCTRL_E 32h 0 1 2 3 4 6..5 7 r/w Function w '0' B1 send data disabled (permanent 1 sent in activated states, reset default) '1' B1 data enabled w '0' B2 send data disabled (permanent 1 sent in activated states, reset default) '1' B2 data enabled w S/T interface mode '0' TE mode (reset default) '1' NT mode w D-channel priority '0' high priority 8/9 (reset default) '1' low priority 10/11 w S/Q bit transmission '0' S/Q bit disable (reset default) '1' S/Q bit and multiframe enable w '0' normal operation (reset default) '1' send 96kHz transmit test signal (alternating zeros) w TX_LO line setup This bit must be configured depending on the used S/T module and circuitry to match the 400 pulse mask test. '0' capacitive line mode (reset default) '1' non capacitive line mode w Power down '0' power up, oscillator active (reset default) '1' power down, oscillator stopped Oscillator is restarted when AWAKE input becomes '1' or on any write access to the HFC-S mini. w force G2 G3 automatic transition from G2 G3 without setting bit 7 of STATES register w must be '0' w D reset '0' normal operation (reset default) '1' D bits are forced to '1' w D_U enable '0' normal operation (reset default) '1' D channel is always send enabled regardless of E receive bit w force E='0' (NT mode) '0' normal operation (reset default) '1' E-bit send is forced to '0' w must be '0' w '1' swap B1 and B2-channel in the S/T interface $$ _V '( 1eWecd " ! 863C ]Y^Y Cologne Chip Name SCTRL_R Addr. 33h Bits 0 1 SQ_REC 34h 7..2 3..0 4 6..5 7 SQ_SEND 34h 3..0 CLKDEL 37h 7..4 3..0 6..4 7 r/w Function w B1-channel receive enable w B2-channel receive enable '0' B-receive bits are forced to '1' '1' normal operation w unused r TE mode: S bits (bit 3 = S1, bit 2 = S2, bit 1 = S3, bit 0 = S4) NT mode: Q bits (bit 3 = Q1, bit 2 = Q2, bit 1 = Q3, bit 0 = Q4) r '1' a complete S or Q multiframe has been received Reading SQ_REC clears this bit. r not defined r '1' ready to send a new S or Q multiframe Writing to SQ_SEND clears this bit. w TE mode: Q bits (bit 3 = Q1, bit 2 = Q2, bit 1 = Q3, bit 0 = Q4) NT mode: S bits (bit 3 = S1, bit 2 = S2, bit 1 = S3, bit 0 = S4) w not defined w TE: 4 bit delay value to adjust the 2 bit time between receive and transmit direction (see also Figure 14). The delay of the external S/T-interface circuit can be compensated. The lower the value the smaller the delay between receive and transmit direction. NT: Data sample point. The lower the value the earlier the input data is sampled. The steps are 163ns. w NT mode only early edge input data shaping Low pass characteristic of extended bus configurations can be compensated. The lower the value the earlier input data pulse is sampled. No compensation means a value of 6 (110b). Step size is the same as for bits 3-0. w unused * note! The register is not initialized with a '0' after reset. The register should be initialized as follows before activating the TE/NT state machine: TE mode: 0Dh .. 0Fh (0Fh for S/T interface circuitry shown on page 59) NT mode: 6Ch 1eWecd " ! $% _V '( 863C ]Y^Y Cologne Chip Name B1_REC *) B1_SEND *) B2_REC *) B2_SEND *) D_REC *) D_SEND *) E_REC *) Addr. 3Ch 3Ch 3Dh 3Dh 3Eh 3Eh 3Fh Bits 7..0 7..0 7..0 7..0 7..0 7..0 7..0 r/w r w r w r w r Function B1-channel receive register B1-channel transmit register B2-channel receive register B2-channel transmit register D-channel receive register D-channel transmit register E-channel receive register *) These registers are read/written automatically by the HDLC FIFO controller (HFC) or PCM controller and need not be accessed by the user. To read/write data the FIFO registers should be used. $& _V '( 1eWecd " ! 863C ]Y^Y Cologne Chip 5 Electrical characteristics Symbol VDD VI VO Topr Tstg Rating -0.3V to +7.0V -0.3V to VCC + 0.3V -0.3V to VCC + 0.3V -10C to +85C -40C to +125C Absolute maximum ratings Parameter Supply voltage Input voltage Output voltage Operating temperature Storage temperature Recommended operating conditions Parameter Supply voltage Operating temperature Supply current normal power down Symbol VDD Topr IDD fCLK=24.576MHz VDD = 3.3V, running oscillator: oscillator stopped: Condition VDD=5V VDD=3.3V MIN. 4.75V 3.0V 0C TYP. 5V 3.3V MAX. 5.25V 3.6V +70C Electrical characteristics for 3.3V power supply VDD = 3.0V to 3.6V, Topr = 0C to +70C Parameter Input LOW voltage Input HIGH voltage Output LOW voltage Output HIGH voltage Schmitt trigger, positive-going threshold Schmitt trigger, negative-going threshold Symbol VIL VIH VOL VOH VT+ Condition MIN. 1.5V TTL level TYP. MAX. 0.8V 0.4V 2.4V 1.3V CMOS level MIN. TYP. MAX. 1.0V 2.0V 0.4V 2.4V 2.0V VT- 0.5V 1.0V 1eWecd " ! $' _V '( 863C ]Y^Y Cologne Chip VDD = 4.75V to 5.25V, Topr = 0C to +70C Electrical characteristics for 5V power supply Parameter Input LOW voltage Input HIGH voltage Output LOW voltage Output HIGH voltage Schmitt trigger, positive-going threshold Schmitt trigger, negative-going threshold Symbol VIL VIH VOL VOH VT+ Condition TTL level MIN. TYP. MAX. 0.8V 2.0V 0.4V 2.4V 2.0V CMOS level MIN. TYP. MAX. 1.5V 3.5V 0.4V 2.4V 4.0V VT- 0.8V 1.0V $( _V '( 1eWecd " ! 863C ]Y^Y Cologne Chip I/O Characteristics Input /RD /WR /CS ALE A0 D0-7 CLKI AWAKE C4IO F0IO STIO1-2 /WAIT /RES Interface Level CMOS CMOS CMOS, internal pull-up resistor CMOS, internal pull-up resistor CMOS CMOS CMOS CMOS TTL Schmitt Trigger, internal pull-up resistor CMOS, internal pull-up resistor CMOS, internal pull-up resistor CMOS, internal pull-up resistor CMOS Schmitt Trigger, internal pull-up resistor Driver Capability Low Output D0-7 C4IO F0IO STIO1-2 F1_A-B /WAIT /INT 0.4V 4mA 8mA 8mA 8mA 4mA 4mA 4mA High VDD - 0.8V 2mA 4mA 4mA 4mA 2mA 1eWecd " ! $) _V '( 863C ]Y^Y Cologne Chip 6 6.1 Timing characteristics Microprocessor access 6.1.1 Register read access in de-multiplexed Motorola mode (mode 2) Timing diagram 1: Register read access in de-multiplexed Motorola mode (mode 2) SYMBOL tRD tRDD tRDDH tSA tSAH tWR tWRDSU tWRDH tCYCLE Read Time CHARACTERISTICS MIN. 50ns 3ns 2ns 20ns 20ns 50ns 30ns 10ns 6x tCLKI MAX. z 25ns 15ns - - /DS Low to Read Data Out Time /DS High to Data Buffer Turn Off Time Address to /DS Low Setup Time Address Hold Time after /DS High Write Time Write Data Setup Time to /DS High Write Data Hold Time from /DS High End of Read Data Cycle to End of Next Read/Write Data Cycle Time z z - z % _V '( 1eWecd " ! 863C ]Y^Y Cologne Chip * hint! If the same register as in the last register read/write access is accessed the register address write is not required. tCLKI is the CLKI clock period. 6.1.2 Register write access in de-multiplexed Motorola mode (mode 2) Timing diagram 2: Register write access in de-multiplexed Motorola mode (mode 2) SYMBOL tSA tSAH tWR tWRDSU tWRDH tCYCLE CHARACTERISTICS Address to /DS Low Setup Time Address Hold Time after /DS High Write Time Write Data Setup Time to /DS High Write Data Hold Time from /DS High End of Write Data Cycle to Start of Next Read/Write Data Cycle Time MIN. 20ns 20ns 50ns 30ns 10ns 6x tCLKI MAX. - - z z - z * hint! If the same register as in the last register read/write access is accessed the register address write is not required. 1eWecd " ! %! _V '( 863C ]Y^Y Cologne Chip 6.1.3 Register read access in de-multiplexed Intel mode (mode 3) Timing diagram 3: Register read access in de-multiplexed Intel mode (mode 3) SYMBOL tRD tRDD tRDDH tSA tSAH tWR tWRDSU tWRDH tCYCLE Read Time CHARACTERISTICS MIN. 50ns 3ns 2ns 20ns 20ns 50ns 30ns 10ns 6x tCLKI MAX. z 25ns 15ns - - /RD Low to Read Data Out Time /RD High to Data Buffer Turn Off Time Address to /RD or /WR Low Setup Time Address Hold Time after /RD or /WR High Write Time Write Data Setup Time to /WR High Write Data Hold Time from /WR High End of Read Data Cycle to End of Next Read/Write Data Cycle Time z z - z * hint! If the same register as in the last register read/write access is accessed the register address write is not required. tCLKI is the CLKI clock period. %" _V '( 1eWecd " ! 863C ]Y^Y Cologne Chip 6.1.4 Register write access in de-multiplexed Intel mode (mode 3) Timing diagram 4: Register write access in de-multiplexed Intel mode (mode 3) SYMBOL tSA tSAH tWR tWRDSU tWRDH tCYCLE CHARACTERISTICS Address to /WR Low Setup Time Address Hold Time after /WR High Write Time Write Data Setup Time to /WR High Write Data Hold Time from /WR High End of Write Data Cycle to Start of Next Read/Write Data Cycle Time MIN. 20ns 20ns 50ns 30ns 10ns 6x tCLKI MAX. - - z z - z * hint! If the same register as in the last register read/write access is accessed the register address write is not required. 1eWecd " ! %# _V '( 863C ]Y^Y Cologne Chip 6.1.5 Register read access in multiplexed mode (mode 4) Timing diagram 5: Register read access in multiplexed mode (mode 4) SYMBOL tRD tRDD tRDDH tSA tSAH tALS tAA tCYCLE Read Time CHARACTERISTICS MIN. 50ns 3ns 2ns 20ns 20ns 30ns 10ns 6 x tCLKI MAX. z 25ns 15ns - - /RD Low to Read Data Out Time /RD High to Data Buffer Turn Off Time Address to ALE Low Setup Time Address Hold Time after ALE Low ALE Low to /RD Low Setup Time ALE Active Time Read/Write Cycle z - z * important! A0 must be '0' during the whole register read cycle. tCLKI is the CLKI clock period. %$ _V '( 1eWecd " ! 863C ]Y^Y Cologne Chip 6.1.6 Register write access in multiplexed mode (mode 4) Timing diagram 6: Register write access in multiplexed mode (mode 4) SYMBOL tWR tWRDSU tWRDH tSA tSAH tALS tAA tCYCLE Write Time CHARACTERISTICS MIN. 50ns 30ns 10ns 20ns 20ns 30ns 10ns 6 x tCLKI MAX. Write Data Setup Time to /WR High Write Data Hold Time from /WR High Address to ALE Low Setup Time Address Hold Time after ALE Low ALE Low to /WR Low Setup Time ALE Active Time Read/Write Cycle z z - - - z - z * important! A0 must be '0' during the whole register write cycle. tCLKI is the CLKI clock period. 1eWecd " ! %% _V '( 863C ]Y^Y Cologne Chip 6.2 PCM/GCI/IOM2 timing Timing diagram 7: PCM/GCI/IOM2 timing *) F0IO starts one C4IO clock earlier if bit 3 in MST_MODE0 register is set. If this bit is set F0IO is also awaited one C4IO clock cycle earlier. If bit 0 (or bit 1) of the MST_MODE2 register is set to '1' a frame signal for OKITM CODECs is generated on F1_A (or F1_B). The C2O clock on F1_A is not available if bit 0 of the MST_MODE2 register is set. If bit 0 (or bit 1) of the MST_MODE2 register is cleared to '0' F1_A (or F1_B) is a CODEC enable signal with the same pulse shape and timing as the F0IO signal. If bits 5..4 of MST_MODE0 are '11' F1_A is C2O clock. **) ***) %& _V '( 1eWecd " ! 863C ]Y^Y Cologne Chip 6.2.1 Master mode To configure the HFC-S mini as PCM/GCI/IOM2 bus master bit 0 of the MST_MODE0 register must be set. In this case C4IO and F0IO are outputs. The PCM bit rate is configured by bits 5..4 of the MST_MODE1 register. SYMBOL tC CHARACTERISTICS for 2Mb/s (PCM30) for 4Mb/s (PCM64) for 8Mb/s (PCM128) tC4P tC4H tC4L tC2P tC2H tC2L tF0iW Clock C4IO period *) Clock C4IO High Width *) Clock C4IO Low Width Clock C2O Period Clock C2O High Width Clock C2O Low Width F0IO Width Short F0IO Long F0IO tSToD tF0iCYCLE STIO1/2 Delay fom C4IO Level 1 Output F0IO Cycle Time 1 half clock adjust 2 half clocks adjust 3 half clocks adjust 4 half clocks adjust All specifications are for fCLK = 24.576 MHz. *) *) MIN. TYP. 122.07 ns 61.035 ns 30.518 ns MAX. 2 tC - 26ns tC - 26ns tC - 26ns 4 tC - 52ns 2 tC - 26ns 2 tC - 26ns 2 tC - 6ns 4 tC - 6ns 2 tC tC tC 4 tC 2 tC 2 tC 2 tC 4 tC 10 ns 2 tC + 26ns tC + 26ns tC + 26ns 4 tC + 52ns 2 tC + 26ns 2 tC + 26ns 2 tC + 6ns 4 tC + 6ns 25 ns 124.975 us 125.000 us 125.025 us 124.950 us 125.000 us 125.050 us 124.925 us 125.000 us 125.075 us 124.900 us 125.000 us 125.100 us Time depends on accuracy of CLKI frequency. Because of clock adjustment in the 31st time slot these are the worst case timings when C4IO is adjusted. 1eWecd " ! %' _V '( 863C ]Y^Y Cologne Chip 6.2.2 Slave mode To configure the HFC-S mini as PCM/GCI/IOM2 bus slave bit 0 of the MST_MODE0 register must be cleared. In this case C4IO and F0IO are inputs. SYMBOL tC CHARACTERISTICS for 2Mb/s (PCM30) for 4Mb/s (PCM64) for 8Mb/s (PCM128) tC4P tC4H tC4L tC2P tC2H tC2L tF0iS tF0iH tF0iW tSTiS Clock C4IO period *) Clock C4IO High Width Clock C4IO Low Width Clock C2O Period *) MIN. TYP. 122.07 ns 61.035 ns 30.518 ns 2 tC MAX. 20 ns 20 ns 4 tC 25 ns 25 ns 20 ns 20 ns 40 ns 20 ns 20 ns Clock C2O High Width Clock C2O Low Width F0IO Setup Time to C4IO F0IO Hold Time after C4IO F0IO Width STIO2 Setup Time tSTiH STIO2 Hold Time All specifications are for fCLK = 24.576 MHz. *) If the S/T interface is synchronized from C4IO (NT mode) the frequency must be stable to 10 -4. %( _V '( 1eWecd " ! 863C ]Y^Y Cologne Chip 7 7.1 External circuitries S/T interface circuitry In order to comply to the physical requirements of ITU-T recommendation I.430 and considering the national requirements concerning overvoltage protection and electromagnetic compatibility (EMC), the HFC-S mini needs some additional circuitry, which are shown in the following figures. 7.1.1 External receiver circuitry W AKE_U P_1 R 20 AD J _LEV C 15 R A1 R1 R B1 LEV_R 1 R 15 R B2 LEV_R 2 R A2 R2 C 16 RC2 RD2 GND D2 GND R EC C 18 I S D N _ S T1 R EC 1 R EC 2 TR A N S 1 TR A N S 2 D1 RC1 RD1 R 14 VD D VD D TR 1 A GND W AKE_U P_2 Figure 10: External receiver circuitry WAKE_UP_1 and WAKE_UP_2 are for connection of the wake up circuitry (see: 7.1.2 External wakeup circuitry). C15 and C16 are for reduction of high frequency input noise and should be placed as close as possible to the HFC-S mini. Part list VDD 3.3V 5V C15 22pF C16 22pF C18 47nF D2 BAV99 D1 BAV99 ISDN_ST1 ISDN Connector RA2 100k RA1 100k RB1 33k RB2 33k VDD RD1 RC1 RD2 RC2 R14 R15 R20 TR1A 3.3V 4k7 4k7 4k7 4k7 680k 1M2 1M 1M8 5V 3k9 S/T Module (see Table 4 on page 63) 1eWecd " ! %) _V '( 863C ]Y^Y Cologne Chip 7.1.2 External wake-up circuitry The wake-up circuitry is optional. It enables the HFC-S mini to wake up by incoming INFOx (non INFO0) signals on the S/T interface. W A K E _U P _2 (from receiver circuitry) R 23 Q3 R 24 W A K E _U P _1 (from receiver circuitry) AW AKE C 17 R 22 (HFC-S mini, pin 28) GN D Figure 11: External wake-up circuitry WAKE_UP_1 and WAKE_UP_2 are inputs from the receiver circuitry (see also: 7.1.1 External receiver circuitry). Part List Part C17 Q3 R22 R23 R24 Value 100pF BC860C 4M7 10k 100k & _V '( 1eWecd " ! 863C ]Y^Y Cologne Chip 7.1.3 External transmitter circuitry VD D R 16 C 14 R 17 R 18 / TX_ E N Q6 R E1 TX1 _ H I Q7 Q8 R E2 TX2 _ H I / TX2 _ L O RG1 Q4 Q5 / TX1 _ L O RG2 RF1 R 19 RF2 GND GND D3 R 21 16 D5 14 D4 GND GND 13 TR 1 B 1 3 4 TR A N S I S D N _ S T1 R EC 1 R EC 2 TR A N S 2 TR A N S 1 Figure 12: External transmitter circuitry Part List VDD 3.3V 5V C14 470pF D3 BAV99 D4 BAV99 D5 2V7 ISDN_ST1 ISDN Connector Q4 BC850C Q5 BC850C Q7 BC850C Q8 BC850C Q6 BC860C RE1 560 1% 2k2 1% RE2 560 1% 2k2 1% *) VDD RF1 RF2 RG1 RG2 R16 R21 R17 R18 R19 TR1B 5V 18 *) 18 *) 3k9 1% 3k 1% 3k9 1% 3k 1% 2k2 3k3 2k2 50 100 3k3 5k6 1k8 3k3 S/T Module (see Table 4 on page 63) 3.3V value is depending on the used S/T module 1eWecd " ! &! _V '( 863C ]Y^Y Cologne Chip S/T module part number APC 56624-1 APC 40495S (SMD) manufacturer Advanced Power Components United Kingdom Phone: +44 1634-290588 +44 1634-290591 S-Hybrid modules with receiver and transmitter Fax: http://www.apcisdn.com circuitry included: APC 5568-3V APC 5568-5V APC 5568DS-3V APC 5568DS-5V FE 8131-55Z FEE GmbH Singapore Phone: +65 741-5277 Fax: +65 741-3013 Bangkok Phone: +662 718-0726-30 Fax: +662 718-0712 Germany Phone: +49 6106-82980 Fax: +49 6106-829898 transformers: Pulse Engineering, Inc. United States PE-64995 Phone: +1-619-674-8100 PE-64999 Fax: +1-619-674-8262 PE-65795 (SMD) http://www.pulseeng.com PE-65799 (SMD) PE-68995 PE-68999 T5006 (SMD) T5007 (SMD) S0-modules: T5012 T5034 T5038 transformers: Sun Myung Korea SM TC-9001 Phone: +82-348-943-8525 SM ST-9002 Fax: +82-348-943-8527 SM ST-16311F http://www.sunmyung.com S0-modules: SM TC-16311 SM TC-16311A transformers UMEC GmbH Germany UT21023 Phone: +49 7131-7617-0 S0-modules: Fax: +49 7131-7617-20 UT 20795 (SMD) Taiwan UT 21624 Phone: +886-4-359-009-6 UT 28624 A Fax: +886-4-359-012-9 United States Phone: +1-310-326-707-2 Fax: +1-310-326-705-8 http://www.umec.de &" _V '( 1eWecd " ! 863C ]Y^Y Cologne Chip manufacturer VAC GmbH Germany Phone: +49 6181/ 38-0 Fax: +49 6181/ 38-2645 http://www.vacuumschmelze.de S/T module part number T 6040... transformers: 3-L4021-X066 3-L4025-X095 3-L5024-X028 3-L4096-X005 3-L5032-X040 S0-modules: 7-L5026-X010 (SMD) 7-L5051-X014 7-M5051-X032 7-L5052-X102 (SMD) 7-M5052-X110 7-M5052-X114 transformers: ST5069 S0-modules: PT5135 ST5201 ST5202 543 76 009 00 503 740 010 0 (SMD) Valor Electronics, Inc. Asia Phone: +852 2333-0127 Fax: +852 2363-6206 North America Phone: +1 800 31VALOR Fax: +1 619 537-2525 Europe Phone: +44 1727-824-875 Fax: +44 1727-824-898 http://www.valorinc.com Vogt electronic AG Germany Phone: +49 8591/ 17-0 Fax: +49 8591/ 17-240 http://www.vogt-electronic.com Table 4: S/T module part numbers and manufacturers 1eWecd " ! &# _V '( 863C ]Y^Y Cologne Chip 7.2 Oscillator circuitry for S/T clock Part List Name R1 R2 C1 C2 Q1 Value 330 1M 47 pF 47 pF 24.576 MHz quarz C LK I C1 24. 576 MH z Q1 GN D R2 C LK O C2 R1 Figure 13: Oscillator circuitry for S/T clock The values of C1, C2 and R1, R2 depend on the used quarz. For a load-free check of the oscillator frequency the C4O clock of the PCM/GCI/IOM2 bus should be measured (HFC-S mini as master, S/T interface deactivated, 4.096 MHz frequency intented on the C4IO). &$ _V '( 1eWecd " ! 863C ]Y^Y Cologne Chip 8 8.1 State matrices for NT and TE S/T interface activation/deactivation layer 1 for finite state matrix for NT State name State number INFO sent Reset G0 Deactive G1 Pending activation G2 Active G3 Pending deactivation G4 Event INFO 0 INFO 0 INFO 2 INFO 4 INFO 0 State machine release (Note 3) G1 | | | | Activate request G2 (Note 1) G2 (Note 1) | | Start timer T2 G4 | Start timer T2 G4 G2 (Note 1) | Deactivate request Expiry T2 (Note 2) Receiving INFO 0 ] ] ] ] ] ] ] G2 (Note 1) / ] ] ] G3 (Note 1) (Note 4) ] G2 G1 G1 Receiving INFO 1 / ] ] Receiving INFO 3 ] Table 5: Activation/deactivation layer 1 for finite state matrix for NT / | No state change Impossible by the definition of peer-to-peer physical layer procedures or system internal reasons Impossible by the definition of the physical layer service Note 1: Timer 1 (T1) is not implemented in the HFC-S mini and must be implemented in software. Note 2: Timer 2 (T2) prevents unintentional reactivation. Its value is 32ms (256 x 125s). This implies that a TE has to recognize INFO 0 and to react on it within this time. Note 3: After reset the state machine is fixed to G0. Note 4: Bit 7 of the STATES register must be set to allow this transition. 1eWecd " ! &% _V '( 863C ]Y^Y Cologne Chip 8.2 Activation/deactivation layer 1 for finite state matrix for TE State name State number Info sent Reset F0 INFO 0 F2 Sensing F2 INFO 0 / | | / Deactivated F3 INFO 0 / F5 F4 Awaiting signal F4 INFO 1 / | | Identifying input F5 INFO 0 / | | Synchronized F6 INFO 3 / Activated F7 INFO 3 / | | Lost framing F8 INFO 0 / Event State machine release (Note 1) Activate Receiving any signal Request Receiving INFO 0 Expiry T3 (Note 5) Receiving INFO 0 Receiving any signal (Note 2) Receiving INFO 2 (Note 3) Receiving INFO 4 (Note 3) Lost framing (Note 4) ] ] ] ] ] ] ] ] ] F3 ] ] ] ] ] F3 F3 / ] F3 F5 F6 F7 / ] ] F3 ] F3 / F6 ] ] ] F3 F6 F7 / F6 F7 / F6 F7 / ] F7 F8 ] F6 F7 ] F8 ] Table 6: Activation/deactivation layer 1 for finite state matrix for TE | / No change, no action Impossible by the definition of the layer 1 service Impossible situation Notes Note 1: After reset the state machine is fixed to F0. Note 2: This event reflects the case where a signal is received and the TE has not (yet) determined wether it is INFO 2 or INFO 4. Note 3: Bit- and frame-synchronisation achieved. Note 4: Loss of Bit- or frame-synchronisation. Note 5: Timer 3 (T3) is not implemented in the HFC-S mini and must be implemented in software. && _V '( 1eWecd " ! 863C ]Y^Y Cologne Chip 9 9.1 Binary organisation of the frames S/T frame structure The frame structures on the S/T interface are different for each direction of transmission. Both structures are illustrated in Figure 14. Figure 14: Frame structure at reference point S and T F L D E FA M Framing bit D.C. balancing bit D-channel bit D-echo-channel bit Auxiliary framing bit Multiframing bit N B1 B2 A S Bit set to a binary value N = F A (NT to TE) Bit within B-channel 1 Bit within B-channel 2 Bit used for activation S-channel bit * note! Lines demarcate those parts of the frame that are independently d.c.-balanced. The FA bit in the direction TE to NT is used as Q bit in every fifth frame if S/Q bit transmission is enabled (see SCTRL register). The nominal 2-bit offset is as seen from the TE. The offset can be adjusted with the CLKDEL register in TE mode. The corresponding offset at the NT may be greater due to delay in the interface cable and varies by configuration. HDLC-B-channel data start with the LSB, PCM-B-channel data start with the MSB. 1eWecd " ! &' _V '( 863C ]Y^Y Cologne Chip 9.2 GCI frame structure The binary organisation of a single GCI channel frame is described below. C4IO clock frequency is 4096kHz. C 4 IO F 0 IO b7 b6 b5 b4 b3 b2 b1 b0 b7 b6 b5 b4 b3 b2 b1 b0 b7 b6 b5 b4 b3 b2 b1 b0 b1 b2 b4 b3 b2 b1 D IN DOUT B1 B2 M D C /I MM RX B1 B1 T im e S lo t 0 T im e S lo t 1 G C I F ra m e T im e S lo t 2 T im e S lo t 3 T im e S lo t 4 T im e S lo t 3 2 Figure 15: Single channel GCI format B1 B2 M D C/I MR MX B-channel 1 data B-channel 2 data Monitor channel data D-channel data Command/indication bits for controlling activation/deactivation and for additional control functions Handshake bit for monitor channel Handshake bit for monitor channel &( _V '( 1eWecd " ! 863C ]Y^Y Cologne Chip 10 Clock synchronisation 10.1 Clock synchronisation in NT-mode Figure 16: Clock synchronisation in NT-mode 1eWecd " ! &) _V '( 863C ]Y^Y Cologne Chip 10.2 Clock synchronisation in TE-mode Figure 17: Clock synchronisation in TE-mode The C4IO clock is adjusted in the 31th time slot at the GCI/IOM bus 1..4 times for one half clock cycle. This can be reduced to one adjustment of a half clock cycle (see MST_MODE1 register). This is useful if another HFC series ISDN controller is connected as slave in NT mode to the PCM bus. The SYNC source can be selected by the MST_MODE2 register settings. ' _V '( 1eWecd " ! 863C ]Y^Y Cologne Chip 10.3 Multiple HFC-S mini SYNC scheme The SYNC scheme for multiple HFC-S mini ISDN controllers is shown in the figure below. The SYNC source of the whole system can be selected by software (see also: MST_MODE2 register bit description). Figure 18: Multiple HFC-S mini SYNC scheme 1eWecd " ! '! _V '( 863C ]Y^Y Cologne Chip 11 HFC-S mini package dimensions Figure 19: HFC-S mini package dimensions '" _V '( 1eWecd " ! 1 2 3 4 5 12.1 V DD C1 U 1A 1eWecd " 26 27 CLKI CLKO S Y N C _I S Y N C _O AW A KE A D J _L E V GND 3 3p Q1 R2 1M A 28 25 W A K E _U P A D J_ LE V S Y N C_ I S Y N C_ O R1 LE V_ R 1 LE V_ R 2 R2 38 43 R1 LEV_R1 LEV_R2 R2 863C ]Y^Y 12 Sample circuitries HFC-S mini in mode 2 (Motorola bus) ! 24 .57 6 C2 R1 3 30 3 3p A0 /D S R/W A0 DS RW W A IT A LE IN T CS RES 23 22 21 20 A GND D0 D1 D2 D3 D4 D5 D6 D7 T X 1_ H I T X2 _L O T X _EN T X1 _L O T X 2_ H I 4 5 6 7 8 9 10 11 D0 D1 D2 D3 D4 D5 D6 D7 17 16 15 14 13 T X 1_ H I /TX 2 _L O /TX _ E N /TX 1 _L O T X 2_ H I 47 1 2 36 45 44 46 48 F 1_A F 1_B ST IO 1 ST IO 2 F 0 IO C 4IO /W A IT /IN T /C S /R E S 34 35 32 33 31 30 F 1_ A F 1_ B S TIO 1 S TIO 2 F 0IO C 4IO H FC S _M IN I_2 B B Processor interface signals JP 1 /D S R /W /C S /IN T A0 U1B VD D VD D VD D VDD C C D0 D1 D2 D3 D4 D5 D6 D7 1 3 5 7 9 11 13 15 17 19 3 19 40 2 4 6 8 10 12 14 16 18 20 to Motorola Processor interface 12 18 24 29 37 39 41 + C3 10 C4 33 n C5 3 3n C6 33 n GND GND GND GND GND GND GND H F C S _M IN I_2 GND GND GND GND GND D D Title M otorola bus w ith control signals /C S ,R /W,/D S S ize A4 D ate: 2 3 D ocum ent N um ber HFCS Mini in Mode 2 Tuesday, A ugust 14, 2001 4 R ev 1.0 S heet 1 5 of 1 1 Cologne Chip '# _V '( '$ _V '( 1 2 3 4 5 VDD R1 C1 RA1 VDD RB1 D1 R3 RB2 RA2 D2 RC2 RD2 C2 GND TR 1A RC1 RD1 R2 A 863C ]Y^Y A A D J_ LE V R1 LE V _R 1 LE V _R 2 R2 B REC GND R4 C4 Q1 R5 IS D N _ ST 1 GND W A K E _U P C6 R8 R6 C7 R7 TRAN S 1 TRAN S 2 REC1 REC2 B VDD R9 Q2 GND remote wake-up (optional) If not used WAKE_UP pin must be grounded. /T X _E N TR 1B C C T X 1 _H I RE1 RG1 R F1 R 11 R F2 D3 GND GND D4 /T X 2_ L O Q5 RG2 Q6 /T X 1_ L O RE2 Q3 Q4 TX 2 _H I TR A N S D5 R12 G ND D D Title G ND M otorola bus w ith control signals /C S ,R /W,/D S D ocum ent Num ber S iz e A4 D a te : 1 2 3 HFCS Mini in Mode 2 Tu e s d a y, A u g u s t 1 4 , 2 0 0 1 4 Rev 1 .0 Sheet 2 5 of 2 Cologne Chip 1eWecd " ! 1 2 3 4 5 C1 GND 33p Q1 2 4 .57 6 1M R1 R2 SYN C_I SYN C_O SY NC_I SY NC_O R1 LEV _R1 LEV _R2 R2 12.2 U1A 26 27 CLKI CLKO AW A K E A D J_ L E V 28 25 W AKE_U P A D J_ L E V R1 LEV_R 1 LEV_R 2 R2 1eWecd " 38 43 23 22 21 20 C2 GND 330 33p A0 /R D /W R A0 RD WR W A IT ALE IN T CS 863C ]Y^Y HFC-S mini in mode 3 (Intel bus with separated address bus/data bus) ! T X 1_ H I TX2_LO TX_E N TX1_LO T X 2_ H I A D0 D1 D2 D3 D4 D5 D6 D7 4 5 6 7 8 9 10 11 D0 D1 D2 D3 D4 D5 D6 D7 17 16 15 14 13 TX1_H I /T X2 _LO /T X_ EN /T X1 _LO TX2_H I A 47 1 2 36 45 44 46 48 RES F1_A F1_B S T IO 1 S T IO 2 F 0IO C 4 IO /W A IT /IN T /C S /R E S 34 35 32 33 31 30 F1_A F1_B S T IO 1 S T IO 2 F 0 IO C 4 IO H FC S _M IN I_2 GND B B Processor interface signals JP 1 /R D /W R /C S /IN T A0 VDD C D0 D1 D2 D3 D4 D5 D6 D7 1 3 5 7 9 11 13 15 17 19 2 4 6 8 10 12 14 16 18 20 C U 1B to Intel non multiplexed Processor interface VDD VDD VDD 3 19 40 + C3 10 C4 33n C5 3 3n C6 33n GND GND GND GND GND GND GND 12 18 24 29 37 39 41 H FC S _M IN I_2 G ND GND GND GND GND D D Title In te l b us w ith se pera te d a dress and da ta bu s, con trol sig nals /C S ,/W R ,/R D S ize A4 D ate: 1 2 3 D ocum en t N u m b er HFCS Mini in Mode 3 Tuesday, A ugust 14, 2 001 4 R ev 1 .0 S hee t 1 5 of 1 Cologne Chip '% _V '( '& _V '( 1 2 3 4 5 VDD R1 C1 RA1 VDD RB1 D1 R3 RB2 RA2 D2 RC2 RD2 C2 GND TR 1A RC1 RD1 R2 A 863C ]Y^Y A A D J_ LE V R1 LE V _R 1 LE V _R 2 R2 B REC GND R4 C4 Q1 R5 IS D N _ ST 1 GND W A K E _U P C6 R8 R6 C7 R7 TRAN S 1 TRAN S 2 REC1 REC2 B VDD R9 Q2 GND remote wake-up (optional) If not used WAKE_UP pin must be grounded. /T X _E N TR 1B C C T X 1 _H I RE1 RG1 R F1 R 11 R F2 D3 GND GND D4 /T X 2_ L O Q5 RG2 Q6 /T X 1_ L O RE2 Q3 Q4 TX 2 _H I TR A N S D5 R12 G ND D D Title G ND In te l b u s w ith s e p e ra te d a d re s s a n d d a ta b u s , c o n tro l s ig n a ls /C S ,/W R ,/R D S iz e A4 D a te : D ocum ent Num ber Rev 1 .0 HFCS Mini in Mode 3 Tu e s d a y, A u g u s t 1 4 , 2 0 0 1 3 4 Sheet 2 5 of 2 1 2 Cologne Chip 1eWecd " ! 1 2 3 4 5 C1 GND 33p Q1 R2 1M R1 2 4.576 SYNC_I SYNC_O S YN C _I S YN C _O R1 LEV _R 1 LEV _R 2 R2 12.3 U 1A 26 27 C LKI C LKO AW A KE A D J_LE V 28 25 W A K E _U P A D J_L E V R1 LE V _ R 1 LE V _ R 2 R2 1eWecd " 38 43 23 22 21 20 C2 GND 3 30 33p /R D /W R /W A IT A LE /IN T /C S /R E S R ES 863C ]Y^Y HFC-S mini in mode 4 (Intel bus with multiplexed address bus/data bus) ! T X 1_H I T X2_ LO T X _E N T X1_ LO T X 2_H I A D0 D1 D2 D3 D4 D5 D6 D7 4 5 6 7 8 9 10 11 D0 D1 D2 D3 D4 D5 D6 D7 17 16 15 14 13 T X 1_ H I /T X 2_L O /T X _E N /T X 1_L O T X 2_ H I A 47 1 2 A0 RD WR W A IT A LE IN T CS F 1_ A F 1_ B S T IO 1 S T IO 2 F 0IO C 4IO 36 45 44 46 48 F 1_ A F 1_ B S T IO 1 S T IO 2 F 0IO C 4IO 34 35 32 33 31 30 H F C S _ M IN I_ 2 GN D B B Processor interface signals JP1 /R D /W R /C S /IN T A LE C D0 D1 D2 D3 D4 D5 D6 D7 U 1B 1 3 5 7 9 11 13 15 17 19 2 4 6 8 10 12 14 16 18 20 VDD C to Intel multiplexed Processor interface VDD VDD VDD 3 19 40 + C3 10 C4 3 3n C5 33 n C6 33n GND GND GND GND GND GND GND 12 18 24 29 37 39 41 H F C S _M IN I_ 2 GND GND GND GND GND D D Title Inte l b us w ith m ultip le xed a dd ress an d d ata b u s S ize A4 D ate : 2 3 D oc um e n t N u m be r HFCS Mini in Mode 4 Tu es da y, A ug us t 1 4, 2 00 1 4 Rev 1.0 S h ee t 1 5 of 1 Cologne Chip 1 '' _V '( '( _V '( 1 2 3 4 5 VDD R1 C1 RA1 VDD RB1 D1 R3 RB2 RA2 D2 RC2 RD2 C2 GN D TR 1 A RC1 RD1 R2 A 863C ]Y^Y A A D J_ LE V R1 L E V _R 1 L E V _R 2 R2 B REC GND R4 C4 R5 IS D N _ S T1 GND WAK E_UP C6 R8 R6 C7 R7 TRANS1 TRANS2 REC1 REC2 B VDD Q1 R9 Q2 GND remote wake-up (optional) If not used WAKE_UP pin must be grounded. /T X _ E N TR 1 B C C TX1_HI RE 1 RG1 R F1 R 11 RF2 D3 GND GND D4 /TX 2_ L O Q5 RG2 Q6 /T X 1 _ L O RE2 Q3 Q4 TX 2_ H I TR A N S D5 R 12 G ND D D Title GND In tel b u s w ith m u ltiplexe d a dd re ss an d da ta bu s D ocu m ent N um be r Size A4 D ate : 1 2 3 HFCS Mini in Mode 4 Tu esd ay, A ug ust 14, 20 01 4 Rev 1 .0 S he et 2 5 of 2 Cologne Chip 1eWecd " ! |
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